LTC2974 [Linear Systems]
Octal Digital Power Supply Manager with EEPROM; 与EEPROM八路数字电源管理器型号: | LTC2974 |
厂家: | Linear Systems |
描述: | Octal Digital Power Supply Manager with EEPROM |
文件: | 总80页 (文件大小:1131K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTC2978
Octal Digital Power Supply
Manager with EEPROM
FEATURES
DESCRIPTION
2
The LTC®2978 is an octal, digital power-supply monitor,
supervisor, sequencer, and margin controller. Eight output
channels can be managed per user defined configura-
tion settings. Supervisory functions include fault OV/UV
threshold limits for eight output channels and one input
channel.Programmablefaultdependenciesandresponses
allow the power supplies to be disabled with optional retry
after a fault has been detected. Serial bus telemetry allows
eight output voltages, one input voltage, die temperature
and fault status to be monitored. In addition, odd num-
bered channels can be configured to measure the voltage
acrossacurrentsenseresistor. Powersupplysequencing,
precisionpoint-of-loadvoltageadjustmentandmargining
are supported with PMBus commands. A programmable
watchdog timer monitors microprocessor activity for a
stalled condition and resets the microprocessor if neces-
sary. The 1-wire synchronization bus supports power
supply sequencing across multiple LTC digital power
devices. User programmable parameters can be stored
in EEPROM. Faults and telemetry data can be logged to
EEPROM for diagnostic analysis.
n
I C/SMBus Serial Interface
n
PMBus Compliant Command Set
n
Configuration EEPROM with CRC
n
Black Box Fault Logging to Internal EEPROM
n
Differential Input, 16-Bit ΔΣ ADC with Less Than
±±.2ꢀ5 of Total Unadjusted Error
n
Eight Voltage Servos Precisely Adjust Output
Voltages Using Eight 1±-Bit DACs with Soft-Connect
n
Monitors Eight Output Voltages and One Input
Voltage and Internal Die Temperature
n
8-Channel Sequencer
n
Programmable Watchdog Timer
n
Eight UV/OV V
and One V Supervisor
OUT
IN
n
n
n
n
Supports Multi-Channel Fault Management
Operates Autonomously without Additional Software
LTC2978 Can Be Powered from 3.3V or 4.ꢀV to 1ꢀV
Available in 64-pin 9mm × 9mm QFN package
APPLICATIONS
n
Computers
n
Network Servers
n
L, LT, LTC, LTM, PolyPhase, Linear Technology and the Linear logo are registered trademarks
and LTpowerPlay ia a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents including 73823±3 and 742±3ꢀ9.
Industrial Test and Measurement
High Reliability Systems
Medical Imaging
Video
n
n
n
TYPICAL APPLICATION
Typical ADC Total Unadjusted
Octal Power Supply Controller with PMBus Interface
Error vs Temperature
0.035
0.030
ADC V = 1.8V
IN
V
4.5V < V
IBUS
< 15V
IN
V
V
V
IN_SNS
V
PWR
OUT
3.3V**
V
DIGITALLY
DD33
DACP0
0.025
MANAGED
POWER
V
R30
SENSEP0
TO INTERMEDIATE
BUS CONVERTER ENABLE
V
IN_EN
R20
R10
0.020
0.015
0.010
0.005
SUPPLY
LTC2978*
V
SDA
LOAD
FB
SCL
V
PMBus
DACM0
INTERFACE
ALERTB
V
SENSEM0
SGND
CONTROL0
WP
V
RUN/SS
OUT_EN0
GND
WRITE-PROTECT
PWRGD
TO µP RESETB INPUT
0
WDI/RESETB
ASEL0
WATCHDOG
–50
–5
25 40 55 70 85 100
–35 –20
10
TIMER INTERRUPT
FAULTB00
TO/FROM OTHER
LTC2978s
TEMPERATURE (°C)
SHARE_CLK
ASEL1
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
2978 TA01b
GND
2978 TA01a
**LTC2978 MAY BE POWERED FROM EITHER AN
EXTERNAL 3.3V SUPPLY OR THE INTERMEDIATE BUS
2978fc
1
LTC2978
TABLE OF CONTENTS
Features..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings.............................. 4
Order Information.......................................... 4
Pin Configuration .......................................... 4
Electrical Characteristics................................. 5
PMBus Timing Diagram................................... 9
Typical Performance Characteristics ..................10
Pin Functions..............................................14
Block Diagram.............................................16
Operation...................................................17
Operation Overview ................................................ 17
EEPROM............................................................. 17
Reset ...................................................................... 18
Write-Protect Pin.................................................... 18
Other Operations .................................................... 18
Clock Sharing ..................................................... 18
PMBus Serial Digital Interface................................ 19
PMBus................................................................ 19
Device Address...................................................22
Processing Commands.......................................23
PMBus Command Summary ............................24
Summary Table...................................................24
Data Formats......................................................28
PMBus Command Description..........................29
Operation, Mode and EEPROM Commands ............29
PAGE ..................................................................29
OPERATION........................................................3±
ON_OFF_CONFIG................................................31
CLEAR_FAULTS..................................................31
WRITE_PROTECT...............................................32
STORE_USER_ALL and RESTORE_USER_ALL .32
CAPABILITY........................................................32
VOUT_MODE ......................................................33
Output Voltage Related Commands........................33
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_
HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_
LIMIT, VOUT_OV_WARN_LIMIT, VOUT_UV_
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_
OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and
VIN_UV_FAULT_LIMIT .......................................33
Temperature Related Commands............................34
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_
LIMIT and UT_FAULT_LIMIT...............................34
Timer Limits ...........................................................34
TON_DELAY, TON_RISE, TON_MAX_FAULT_
LIMIT and TOFF_DELAY......................................34
Fault Response for Voltages Measured by the High
Speed Supervisor ...................................................3ꢀ
VOUT_OV_FAULT_RESPONSE and VOUT_UV_
FAULT_RESPONSE .............................................3ꢀ
Fault Response for Values Measured by the ADC ...36
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE,
VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_
RESPONSE .........................................................36
Timed Fault Response ............................................36
TON_MAX_FAULT_RESPONSE..........................36
Status Commands ..................................................37
STATUS_BYTE:...................................................37
STATUS_WORD:.................................................38
STATUS_VOUT ...................................................38
STATUS_INPUT..................................................39
STATUS_TEMPERATURE....................................39
STATUS_CML .....................................................4±
STATUS_MFR_SPECIFIC....................................4±
ADC Monitoring Commands................................... 41
READ_VIN .......................................................... 41
READ_VOUT....................................................... 41
READ_TEMPERATURE_1 .................................. 41
PMBUS_REVISION............................................. 41
Manufacturer Specific Commands..........................42
MFR_CONFIG_LTC2978.....................................42
MFR_CONFIG_ALL_LTC2978 ............................43
MFR_FAULTz±_PROPAGATE, MFR_FAULTz1_
PROPAGATE .......................................................44
MFR_PWRGD_EN ..............................................4ꢀ
MFR_FAULTB±±_RESPONSE, MFR_FAULTB±1_
RESPONSE, MFR_FAULTB1±_RESPONSE and
MFR_FAULTB11_RESPONSE..............................46
MFR_VINEN_OV_FAULT_RESPONSE.................47
MFR_VINEN_UV_FAULT_RESPONSE.................48
WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_
GOOD_ON and POWER_GOOD_OFF ..................33
Input Voltage Related Commands...........................33
2978fc
2
LTC2978
TABLE OF CONTENTS
MFR_RETRY_DELAY..........................................48
MFR_RESTART_DELAY......................................49
MFR_VOUT_PEAK ..............................................49
MFR_VIN_PEAK .................................................49
MFR_TEMPERATURE_PEAK..............................49
MFR_DAC...........................................................ꢀ±
MFR_POWERGOOD_ASSERTION_DELAY .........ꢀ±
Watchdog Operation...............................................ꢀ±
MFR_WATCHDOG_T_FIRST and MFR_
V
Off Threshold Voltage................................64
OUT
Automatic Restart Via MFR_RESTART_DELAY
Command and CONTROLn pin ...........................64
Fault Management ..................................................64
Output Overvoltage and Undervoltage Faults .....64
Output Overvoltage and Undervoltage Warnings6ꢀ
Configuring the V
Output............................6ꢀ
IN_EN
Multichannel Fault Management ........................67
Interconnect Between Multiple LTC2978s...............67
Application Circuits.................................................69
Trimming and Margining DC/DC Converters with
External Feedback Resistors...............................69
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors.....69
Trimming and Margining DC/DC Converters with a
TRIM Pin ............................................................7±
Two-Step Resistor and DAC Full-Scale Voltage
Selection Procedure for DC/DC Converters with a
TRIM Pin ............................................................7±
Measuring Current..............................................71
Measuring Current with a Sense Resistor...........71
Measuring Current with Inductor DCR................71
Single Phase Design Example ............................72
Measuring Multiphase Currents..........................72
Multiphase Design Example ...............................72
Anti-aliasing Filter Considerations ......................73
Sensing Negative Voltages .................................73
WATCHDOG_T ....................................................ꢀ±
MFR_PAGE_FF_MASK ....................................... ꢀ1
MFR_PADS.........................................................ꢀ2
MFR_I2C_BASE_ADDRESS ...............................ꢀ2
MFR_SPECIAL_ID..............................................ꢀ2
MFR_SPECIAL_LOT...........................................ꢀ3
MFR_VOUT_DISCHARGE_THRESHOLD.............ꢀ3
MFR_COMMON..................................................ꢀ3
MFR_SPARE±.....................................................ꢀ3
MFR_SPARE2.....................................................ꢀ3
MFR_VOUT_MIN ................................................ꢀ4
MFR_VIN_MIN ...................................................ꢀ4
MFR_TEMPERATURE_MIN ................................ꢀ4
Fault Log Operation ................................................ꢀ4
MFR_FAULT_LOG_STORE .................................ꢀꢀ
MFR_FAULT_LOG_RESTORE.............................ꢀꢀ
MFR_FAULT_LOG_CLEAR..................................ꢀꢀ
MFR_FAULT_LOG_STATUS................................ꢀꢀ
MFR_FAULT_LOG...............................................ꢀ6
Applications Information ................................62
Overview.................................................................62
Powering the LTC2978............................................62
Setting Command Register Values .........................62
Sequence, Servo, Margin and Restart Operations ..62
Command Units On or Off..................................62
On Sequencing ...................................................63
On State Operation .............................................63
Servo Modes ......................................................63
DAC Modes.........................................................63
Margining ...........................................................64
Off Sequencing...................................................64
2
Connecting the USB to I C/SMBus/PMBus Controller
to the LTC2978 in System....................................... 74
LTpowerPlay: An Interactive GUI for Digital Power .76
PCB Assembly and Layout Suggestions .................77
Bypass Capacitor Placement ..............................77
Exposed Pad Stencil Design...............................77
PC Board Layout.................................................77
Unused ADC Sense Inputs..................................77
Package Description .....................................78
Revision History ..........................................79
Typical Application .......................................80
Related Parts..............................................80
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3
LTC2978
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltages:
TOP VIEW
V
V
V
V
to GND ......................................... –±.3V to 1ꢀV
PWR
IN_SNS
DD33
DD2ꢀ
to GND...................................... –±.3V to 1ꢀV
to GND ....................................... –±.3V to 3.6V
to GND ..................................... –±.3V to 2.7ꢀV
V
V
V
V
V
V
V
V
1
2
3
4
5
6
7
8
9
48 V
47 V
46 V
45 V
44 V
43 V
42 V
41 V
40 V
39 V
38 V
37 V
36 V
SENSEM6
SENSEP3
SENSEM2
SENSEP2
DACM2
Digital Input/Output Voltages:
V
SENSEP7
SENSEM7
ALERTB, SDA, SCL, CONTROL±,
CONTROL1............................................ –±.3V to ꢀ.ꢀV
PWRGD, SHARE_CLK,
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
OUT_EN4
OUT_EN5
DACP2
SENSEM1
SENSEP1
DACM1
WDI/RESETB, WP....................–±.3V to V
FAULTB±±, FAULTB±1, FAULTB1±,
FAULTB11 ................................–±.3V to V
ASEL±, ASEL1..........................–±.3V to V
Analog Voltages:
+ ±.3V
DD33
65
DACP1
V
10
11
12
OUT_EN6
DACP0
V
+ ±.3V
+ ±.3V
OUT_EN7
DACM0
DD33
DD33
V
IN_EN
SENSEM0
SENSEP0
DNC 13
V
14
15
16
35 REFM
34 REFP
33 ASEL1
IN_SNS
V
PWR
REFP................................................... –±.3V to 1.3ꢀV
REFM to GND........................................ –±.3V to ±.3V
V
DD33
V
V
V
V
V
V
to GND................................. –±.3V to 6V
to GND ................................ –±.3V to 6V
OUT_EN[3:±] IN_EN
SENSEP[7:±]
SENSEM[7:±]
, V
to GND .................. –±.3V to 1ꢀV
UP PACKAGE
to GND................................. –±.3V to 6V
OUT_EN[7:4]
DACP[7:±]
DACM[7:±]
64-LEAD (9mm × 9mm) PLASTIC QFN
to GND .................................... –±.3V to 6V
T
JMAX
= 12ꢀ°C, θ
= 7°C/W, θ
= 1°C/W
JC-BOTTOM
JC-TOP
EXPOSED PAD (PIN 6ꢀ) IS GND, MUST BE SOLDERED TO PCB
to GND ................................ –±.3V to ±.3V
Operating Junction Temperature Range:
LTC2978C................................................ ±°C to 7±°C
LTC2978I .............................................–4±°C to 8ꢀ°C
Storage Temperature Range .................. –6ꢀ°C to 12ꢀ°C
ORDER INFORMATION
LEAD FREE FINISH
LTC2978CUP#PBF
LTC2978IUP#PBF
TAPE AND REEL
PART MARKING*
LTC2978UP
PACKAGE DESCRIPTION
TEMPERATURE RANGE JUNCTION
±°C to 7±°C
LTC2978CUP#TRPBF
LTC2978IUP#TRPBF
64-Lead (9mm × 9mm) Plastic QFN
64-Lead (9mm × 9mm) Plastic QFN
LTC2978UP
–4±°C to 8ꢀ°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2978fc
4
LTC2978
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V, VDD33, VDD25 and REF pins floating, unless
otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Supply Characteristics
l
l
l
l
V
V
V
V
V
V
Supply Input Operating Range
Supply Current
4.ꢀ
1ꢀ
13
13
2.8
V
mA
mA
V
PWR
PWR
PWR
DD33
DD33
DD33
I
I
4.ꢀV ≤ V
≤ 1ꢀV, V
Floating
DD33
1±
1±
PWR
PWR
Supply Current
3.13V ≤ V
≤ 3.47V, V
= V
PWR
VDD33
DD33
DD33
DD33
V
Undervoltage Lockout
Undervoltage Lockout
Hysteresis
V
Ramping Up, V = V
PWR
2.3ꢀ
2.ꢀꢀ
12±
UVLO_VDD33
DD33
mV
l
l
l
l
l
V
Supply Input Operating Range
Regulator Output Voltage
V
= V
3.13
3.13
7ꢀ
3.47
3.47
14±
2.6
V
V
DD33
PWR
DD33
4.ꢀV ≤ V
≤ 1ꢀV
3.26
9±
PWR
Regulator Output Short-Circuit Current
Regulator Output Voltage
V
PWR
= 4.ꢀV, V
= ±V
DD33
mA
V
V
3.13V ≤ V
≤ 3.47V
2.3ꢀ
3±
2.ꢀ
ꢀꢀ
DD2ꢀ
DD33
DD33
Regulator Output Short-Circuit Current
V
PWR
= V
= 3.47V, V
= ±V
8±
mA
DD2ꢀ
Voltage Reference Characteristics
V
REF
Output Voltage
1.232
3
V
ppm/°C
ppm
Temperature Coefficient
Hysteresis
(Note 3)
1±±
ADC Characteristics
l
V
Voltage Sense Input Range
Differential Voltage:
= (V
±
6
V
IN_ADC
V
– V
)
IN_ADC
SENSEPn
SENSEMn
l
l
l
Single-Ended Voltage: V
Single-Ended Voltage: V
–±.1
–±.1
–17±
±.1
6
V
V
SENSEMn
Current Sense Input Range (Odd
Numbered Channels Only)
, V
SENSEPn SENSEMn
Differential Voltage: V
17±
mV
IN_ADC
N_ADC
Voltage Sense Resolution Uses L16
Format
±V ≤ V ≤ 6V
122
µV/LSB
IN_ADC
Current Sense Resolution (Odd
Numbered Channels Only)
±mV ≤ |V
| < 16mV (Note13)
1ꢀ.62ꢀ
31.2ꢀ
62.ꢀ
µV/LSB
µV/LSB
µV/LSB
µV/LSB
µV/LSB
IN_ADC
16mV ≤ |V
32mV ≤ |V
| < 32mV
IN_ADC
IN_ADC
IN_ADC
| < 63.9mV
63.9mV ≤ |V
127.9mV ≤ |V
| < 127.9mV
12ꢀ
|
2ꢀ±
IN_ADC
l
l
l
TUE_ADC
INL_ADC
Total Unadjusted Error
Integral Nonlinearity
V
≥ 1.8V (Note 4 )
±±.2ꢀ
±8ꢀ4
±31.3
5
µV
µV
IN_ADC
Voltage Sense Mode (Note ꢀ)
Current Sense Mode, Odd Numbered
Channels Only, 1ꢀ.6µV/LSB (Note ꢀ)
l
l
DNL_ADC
Differential Nonlinearity
Offset Error
Voltage Sense Mode
±4±±
µV
µV
Current Sense Mode, Odd Numbered
Channels Only
±31.3
l
l
V
Voltage Sense Mode
±2ꢀ±
±3ꢀ
µV
µV
OS_ADC
Current Sense Mode, Odd Numbered
Channels Only
l
l
GAIN_ADC
Gain Error
Voltage Sense Mode, V
= 6V
±±.2
±±.2
5
5
IN_ADC
Current Sense Mode, Odd Numbered
Channels Only, V = ±±.17V
IN_ADC
2978fc
5
LTC2978
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless
otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
6.1ꢀ
24.6
24.6
1
MAX
UNITS
ms
t
Conversion Time
Voltage Sense Mode (Note 6)
Current Sense Mode (Note 6)
Temperature Input (Note 6)
CONV_ADC
ms
ms
C
Input Sampling Capacitance
Input Sampling Frequency
Input Leakage Current
pF
IN_ADC
IN_ADC
IN_ADC
f
I
62.ꢀ
kHz
µA
l
V
= ±V, ±V ≤ V
≤ 6V,
COMMONMODE
±±.ꢀ
IN_ADC
Current Sense Mode
l
l
Differential Input Current
V
V
= ±.17V, Current Sense Mode
= 6V, Voltage Sense Mode
8±
1±
2ꢀ±
1ꢀ
nA
µA
IN_ADC
IN_ADC
Voltage Buffered IDAC Output Characteristics
N_V
Resolution
1±
Bits
DACP
l
l
V
Full-Scale Output Voltage
(Programmable)
DAC Code = ±x3FF Buffer Gain Setting_±
1.32
2.ꢀ3
1.38
2.6ꢀ
1.44
2.77
V
V
FS_VDACP
DAC Polarity = 1
Buffer Gain Setting_1
l
l
l
INL_V
Integral Nonlinearity
Differential Nonlinearity
Offset Voltage
(Note 7)
±2
LSB
LSB
mV
DACP
DNL_V
(Note 7)
±2.4
±1±
DACP
OS_VDACP
DACP
V
V
(Note 7)
Load Regulation (V
– V
)
V
DACPn
V
DACPn
= 2.6ꢀV, I Sourcing = 2mA
VDACPn
1±±
1±±
6±
ppm/mA
ppm/mA
dB
DACPn
DACMn
= ±.1V, I
Sinking = 2mA
VDACPn
PSRR (V
– V
)
DC: 3.13V ≤ V
≤ 3.47V, V
= V
PWR DD33
DACPn
DACMn
DD33
1±±mV Step in 2±ns with ꢀ±pF Load
–±.1V ≤ V ≤ ±.1V
4±
dB
DC CMRR (V
– V
)
6±
dB
DACPn
DACMn
DACMn
l
l
l
Leakage Current
V
DACPn
V
DACPn
V
DACPn
V
DACPn
Hi-Z, ±V ≤ V
≤ 6V
±1±±
–4
nA
DACPn
Short-Circuit Current Low
Short-Circuit Current High
Output Capacitance
Shorted to GND
–1±
4
mA
Shorted to V
Hi-Z
1±
mA
DD33
C
OUT
1±
pF
t
DAC Output Update Rate
Fast Servo Mode
2ꢀ±
µs
S_VDACP
Voltage Supervisor Characteristics
l
l
V
IN_VS
Input Voltage Range (Programmable)
V
= (V
SENSEMn
Low Resolution Mode
High Resolution Mode
±
±
6
3.8
V
V
IN_VS
SENSEPn
)
– V
l
Single-Ended Voltage: V
–±.1
±.1
V
mV/LSB
mV/LSB
5
SENSEMn
N_VS
Voltage Sensing Resolution
Total Unadjusted Error
±V to 3.8V Range: High Resolution Mode
±V to 6V Range: Low Resolution Mode
4
8
l
l
l
TUE_VS
2V ≤ V
≤ 6V, Low Resolution Mode
±1.2ꢀ
±1.±
±1.ꢀ
IN_VS
1.ꢀV < V
±.8V ≤ V
≤ 3.8V, High Resolution Mode
≤ 1.ꢀV, High Resolution Mode
5
IN_VS
IN_VS
5
t
Update Rate
12.21
9±
µs
S_VS
V
Input Characteristics
IN_SNS
l
l
V
V
Input Voltage Range
±
1ꢀ
V
VIN_SNS
IN_SNS
IN_SNS
R
V
Input Resistance
7±
11±
kΩ
VIN_SNS
2978fc
6
LTC2978
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless
otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
TUE
PARAMETER
, V
CONDITIONS
3V ≤ V
VIN_SNS
MIN
TYP
MAX
±2.±
±1.±
±1.ꢀ
±1.±
UNITS
5
l
l
l
l
V
Threshold Total
≤ 8V
≤ 8V
VIN_SNS
IN_ON IN_OFF
Unadjusted Error
V
> 8V
5
VIN_SNS
READ_V Total Unadjusted Error
3V ≤ V
5
IN
VIN_SNS
V
> 8V
5
VIN_SNS
Voltage Buffered IDAC Soft-Connect Comparator Characteristics
Offset Voltage
Temperature Sensor Characteristics
TUE_TS Total Unadjusted Error
l
V
±3
±1
±18
mV
°C
OS_CMP
V
OUT
Enable Output (V
[3:0]) Characteristics
OUT_EN
l
l
l
V
Output High Voltage (Note 12)
I
= –ꢀµA, V = 3.3V
DD33
11.6
–ꢀ
3
12.ꢀ
–6
ꢀ
14.7
–8
8
V
µA
VOUT_ENn
VOUT_ENn
VOUT_ENn
I
Output Sourcing Current
Output Sinking Current
V
Pull-Up Enabled, V
= 1V
VOUT_ENn
VOUT_ENn
Strong Pull-Down Enabled,
= ±.4V
mA
V
VOUT_ENn
l
l
Weak Pull-Down Enabled, V
= ±.4V
33
ꢀ±
6±
±1
µA
µA
VOUT_ENn
Output Leakage Current
Internal Pull-Up Disabled,
±V ≤ V
≤ 1ꢀV
VOUT_ENn
V
Enable Output (V
[7:4]) Characteristics
OUT
OUT_EN
l
l
I
Output Sinking Current
Strong Pull-Down Enabled,
OUT_ENn
3
6
9
mA
µA
VOUT_ENn
V
= ±.1V
Output Leakage Current
±V ≤ V
≤ 6V
±1
VOUT_ENn
V
Enable Output (V ) Characteristics
IN_EN
IN
l
l
l
l
V
Output High Voltage
Output Sourcing Current
Output Sinking Current
Leakage Current
I
= –ꢀµA, V = 3.3V
DD33
11.6
–ꢀ
3
12.ꢀ
–6
ꢀ
14.7
–8
8
V
µA
VIN_EN
VIN_EN
VIN_EN
I
V
V
Pull-Up Enabled, V
= 1V
IN_EN
VIN_EN
= ±.4V
mA
µA
VIN_EN
Internal Pull-Up Disabled,
±V ≤ V ≤ 1ꢀV
±1
VIN_EN
EEPROM Characteristics
l
Endurance
(Notes 8, 11)
±°C < T < 8ꢀ°C During EEPROM Write
1±,±±±
1±
Cycles
J
Operations
l
l
Retention
(Notes 8, 11)
T < 8ꢀ°C
J
Years
ms
Mass_Write Mass Write Operation Time (Note 9)
STORE_USER_ALL, ±°C < T < 8ꢀ°C During
44±
2±
41±±
1.ꢀ
J
EEPROM Write Operations
Digital Inputs SCL, SDA, CONTROL0, CONTROL1, WDI/RESETB, FAULTB00, FAULTB01, FAULTB10, FAULTB11, WP
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
2.1
V
V
IH
l
IL
mV
µA
HYST
LEAK
l
l
I
Input Leakage Current
±V ≤ V ≤ ꢀ.ꢀV, SDA, SCL, CONTROLx
±2
±2
PIN
Pins Only
±V ≤ V ≤ V
+ ±.3V, FAULTBxx,
µA
PIN
DD33
WDI/RESETB, WP Pins Only
FAULTBxx, CONTROLx Pins Only
SDA, SCL Pins Only
t
t
Pulse Width of Spike Suppressed
1±
98
µs
ns
SP
Minimum Low Pulse Width for
Externally Generated Faults
11±
ms
FAULT_MIN
2978fc
7
LTC2978
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TJ = 25°C. VPWR = VIN_SNS = 12V; VDD33, VDD25 and REF pins floating, unless
otherwise indicated. CVDD33 = 100nF, CVDD25 = 100nF and CREF = 100nF.
SYMBOL
PARAMETER
CONDITIONS
MIN
3±±
±.3
TYP
MAX
UNITS
µs
l
l
l
t
t
f
Pulse Width to Assert Reset
Pulse Width to Reset Watchdog Timer
Watchdog Interrupt Input Frequency
Digital Input Capacitance
V
V
≤ 1.ꢀV
≤ 1.ꢀV
RESETB
WDI
WDI/RESETB
WDI/RESETB
2±±
1
µs
MHz
pF
WDI
C
1±
IN
Digital Input SHARE_CLK
l
l
l
l
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Frequency Operating Range
Assertion Low Time
Rise Time
1.6
V
V
IH
±.8
11±
1.1
4ꢀ±
±1
IL
f
t
t
I
9±
kHz
µs
SHARE_CLK_IN
LOW
V
V
< ±.8V
±.82ꢀ
SHARE_CLK
< ±.8V to V
> 1.6V
ns
RISE
SHARE_CLK
SHARE_CLK
Input Leakage Current
Input Capacitance
±V ≤ V
≤ V + ±.3V
DD33
µA
pF
LEAK
SHARE_CLK
C
1±
IN
Digital Outputs SDA, ALERTB, PWRGD, SHARE_CLK, FAULTB00, FAULTB01, FAULTB10, FAULTB11
l
l
V
Digital Output Low Voltage
I
= 3mA
±.4
V
OL
SINK
f
Output Frequency Operating Range
ꢀ.49kΩ Pull-Up to V
9±
1±±
11±
kHz
SHARE_CLK_OUT
DD33
Digital Inputs ASEL0,ASEL1
l
l
l
l
V
V
Input High Threshold Voltage
Input Low Threshold Voltage
High, Low Input Current
Hi-Z Input Current
V
DD33
– ±.ꢀ
V
V
IH
±.ꢀ
±9ꢀ
±24
IL
I
I
ASEL[1:±] = ±, V
µA
µA
pF
IH,IL
IH, Z
DD33
C
Input Capacitance
1±
IN
Serial Bus Timing Characteristics
l
l
l
l
f
t
t
t
Serial Clock Frequency (Note 1±)
Serial Clock Low Period (Note 1±)
Serial Clock High Period (Note 1±)
1±
1.3
±.6
1.3
4±±
kHz
µs
SCL
LOW
HIGH
BUF
µs
Bus Free Time Between Stop and Start
(Note 1±)
µs
l
l
l
l
t
t
t
t
Start Condition Hold Time (Note 1±)
Start Condition Setup Time (Note 1±)
Stop Condition Setup Time (Note 1±)
6±±
6±±
6±±
±
ns
ns
ns
ns
HD,STA
SU,STA
SU,STO
HD,DAT
Data Hold Time (LTC2978 Receiving
Data) (Note 1±)
l
l
Data Hold Time (LTC2978 Transmitting
Data) (Note 1±)
3±±
1±±
9±±
ns
t
t
Data Setup Time (Note 1±)
ns
ns
SU,DAT
Pulse Width of Spike Suppressed
(Note 1±)
98
SP
l
l
t
Time Allowed to Complete any PMBus Longer Timeout = ±
Command After Which Time SDA Will Longer Timeout = 1
Be Released and Command Terminated
2ꢀ
2±±
3ꢀ
28±
ms
ms
TIMEOUT_BUS
2978fc
8
LTC2978
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating for extended periods may affect device reliability and lifetime.
Note 7: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1±23.
Note 8: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified. If power is supplied to the chip via the V
pin only, connect
DD33
V
and V
pins together.
PWR
DD33
Note 9: The LTC2978 will not acknowledge any PMBus commands while a
mass write operation is being executed. This includes the STORE_USER_ALL
and MFR_FAULT_LOG_STORE commands or a fault log store initiated by a
channel faulting off.
Note 3: Hysteresis in the output voltage is created by package stress that
differs depending on whether the IC was previously at a higher or lower
temperature. Output voltage is always measured at 2ꢀ°C, but the IC is
cycled to 8ꢀ°C or –4±°C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 10: Maximum capacitive load, C , for SCL and SDA is 4±±pF. Data
B
and clock rise time (t ) and fall time (t )ꢀare:ꢀ(20ꢀ+ꢀ0.1ꢀ•ꢀC ) (ns) < t < 3±±ns
r
f
B
r
Note 4: TUE(5) is defined as:
andꢀ(20ꢀ+ꢀ0.1ꢀ•ꢀC ) (ns) < t < 3±±ns. C = capacitance of one bus line in pF.
B f B
SCL and SDA external pull-up voltage, V , is 3.13V < V < ꢀ.ꢀV.
IO
IO
ꢀ
GainꢀErrorꢀ(%)ꢀ+ꢀ100ꢀ•ꢀ(INLꢀ+ꢀV )/V .
OS IN
Note 11: EEPROM endurance and retention will be degraded when T > 8ꢀ°C.
J
Note 5: Integral nonlinearity (INL) is defined as the deviation of a code
from a straight line passing through the actual endpoints of the transfer
curve (±V and 6V). The deviation is measured from the center of the
quantization band.
Note 6: The time between successive ADC conversions (latency of the
ADC)ꢀforꢀanyꢀgivenꢀchannelꢀisꢀgivenꢀas:ꢀ36.9msꢀ+ꢀ(6.15msꢀ•ꢀnumberꢀofꢀ
ADCꢀchannelsꢀconfiguredꢀinꢀLowꢀResolutionꢀmode)ꢀ+ꢀ(24.6msꢀ•ꢀnumberꢀofꢀ
ADC channels configured in High Resolution mode).
Note 12: Output enable pins are charge pumped from V
.
DD33
Note 13: The current sense resolution is determined by the L11 format
and the mV units of the returned value. For example a full scale value
–2
ofꢀ170mVꢀreturnsꢀaꢀL11ꢀvalueꢀofꢀ0xF2A8ꢀ=ꢀ680ꢀ•ꢀ2 = 17±. This is the
lowest range that can represent this value without overflowing the L11
–2
mantissa and the resolution for 1LSB in this range is 2 mV = 2ꢀ±µV.
Each successively lower range improves resolution by cutting the LSB size
in half.
PMBUS TIMING DIAGRAM
SDA
t
r
t
SU(DAT)
t
t
SP
t
r
HD(SDA)
t
t
t
t
f
BUF
f
LOW
SCL
t
t
t
SU(STO)
HD(STA)
SU(STA)
t
t
HIGH
HD(DAT)
2978 TD
START
CONDITION
REPEATED START
CONDITION
STOP
START
CONDITION CONDITION
2978fc
9
LTC2978
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Total Unadjusted Error
vs Temperature
Temperature Sensor Error
Reference Voltage vs Temperature
vs Temperature
1.2355
1.2350
1.2345
1.2340
1.2335
1.2330
1.2325
1.2320
1.2315
1.2310
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.035
0.030
ADC V = 1.8V
IN
0.025
0.020
0.015
0.010
0.005
THREE TYPICAL PARTS
0
–50 –35 –20 –5 10 25
100
–50 –35 –20 –5 10 25 40 55 70 85 100
–50
–5
55
100
70 85
40 55 70 85
–35 –20
10 25 40
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
2978 G01
2978 G02
2978 G03
ADC Zero Code Center Offset
Voltage vs Temperature
ADC-INL
ADC-DNL
0.8
0.6
0
–20
3.0
2.5
2.0
1.5
1.0
0.5
0
VOLTAGE SENSE MODE
122µV/LSB
122µV/LSB
0.4
–40
0.2
–60
0
–80
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–120
–140
–160
–180
–0.5
–1.0
–1.5
–0.2 0.8
1.8
2.8
3.8
4.8
–50 –35 –20 –5 10 25
100
–0.2 0.8
1.8
2.8
3.8
4.8
5.8
40 55 70 85
5.8
INPUT VOLTAGE (V)
TEMPERATURE (°C)
INPUT VOLTAGE (V)
2978 G06
2978 G04
2978 G05
ADC Rejection
vs Frequency at VIN
ADC Rejection
vs Frequency at VIN (Zoom)
ADC Rejection vs Frequency
at VIN (Current Sense Mode)
0
0
0
–20
–20
–20
–40
–60
–40
–60
–40
–60
–80
–100
–120
–80
–100
–120
–80
–100
–120
0
12500 25000 37500 50000 62500
FREQUENCY (Hz)
0
3125
6250
FREQUENCY (Hz)
9375
12500
0
12500 25000 37500 50000 62500
FREQUENCY (Hz)
2978 G07
2978 G08
2978 G09
2978fc
10
LTC2978
TYPICAL PERFORMANCE CHARACTERISTICS
ADC Rejection vs Frequency
Voltage Supervisor Total
Unadjusted Error vs Temperature
ADC Noise Histogram
at VIN (Current Sense Mode, Zoom)
1200
1000
0
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–0.35
–0.40
V
IN
= 0V
V
= 0.8V
IN
HIGH RESOLUTION MODE
HIGH RESOLUTION MODE
–20
800
600
–40
–60
400
200
0
–80
–100
–120
–20
–10
0
10
20
0
3125
6250
9375
12500
–50 –35 –20 –5 10 25 40 55 70 85 100
READ_V
(µV)
FREQUENCY (Hz)
OUT
TEMPERATURE (°C)
2978 G11
2978 G10
2978 G12
DAC Full-Scale Output Voltage vs
Temperature
Input Sampling Current
vs Differential Input Voltage
ADC High Resolution Mode
Differential Input Current
2.698
9
8
7
6
5
4
3
2
1
90
80
70
60
50
40
30
20
10
2.696
2.694
2.692
2.690
2.688
2.686
2.684
2.682
2.680
2.678
0
0
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE (°C)
0
1
2
3
6
4
5
0
20 40 60 80 100
180
120 140 160
INPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (mV)
2978 G15
2978 G13
2978 G14
DAC Offset Voltage vs
Temperature
DAC-INL
DAC DNL
1.0
0.8
1.0
0.8
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
200
400
600
800
1000
0
200
400
600
800
1000
–50 –35 –20 –5 10 25 40 55 70 85 100
DAC CODE
DAC CODE
TEMPERATURE (°C)
2978 G17
2978 G18
2978 G16
2978fc
11
LTC2978
TYPICAL PERFORMANCE CHARACTERISTICS
DAC Short-Circuit Current vs
Temperature
DAC Load Regulation (Sourcing)
DAC Load Regulation (Sinking)
2.698
2.696
2.694
2.692
2.690
2.688
2.686
2.684
2.682
2.680
2.678
9.00
8.95
0.1038
0.1036
0.1034
0.1032
0.1030
0.1028
0.1026
85°C
85°C
25°C
25°C
8.90
8.85
8.80
8.75
8.70
–40°C
–40°C
0
–1
–1.50 1.75
–50 –35 –20 –5 10 25 40 55 70 85 100
TEMPERATURE (°C)
–0.25 –0.5 –0.75
–1.25
–2
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
CURRENT (mA)
CURRENT (mA)
2978 G19
2978 G21
2978 G20
DAC Soft Connect Transient
Response when Transitioning from
Hi-Z State to ON State
DAC Soft Connect Transient
Response when Transitioning from
ON State to Hi-Z State
DAC Transient Response to 1LSB
DAC Code Change
CODE ‘h200
HI-Z
HI-Z
500µV/DIV
10mV/DIV
10mV/DIV
CONNECTED
CONNECTED
CODE ‘h1FF
2978 G22
2978 G24
2978 G23
2µs/DIV
500µs/DIV
500µs/DIV
100k SERIES RESISTANCE ON
CODE: ‘h1FF
100k SERIES RESISTANCE ON
CODE: ‘h1FF
VDD33 Regulator Output Voltage
vs Temperature
VDD33 Regulator Short-Circuit
Current vs Temperature
VDD33 Regulator Line Regulation
3.275
3.270
3.265
3.260
3.255
3.250
3.245
3.240
3.235
–86
–88
400
300
85°C
25°C
200
–90
100
–92
–40°C
0
–94
–100
–200
–300
–400
–96
–98
–100
–102
–500
–50 –35 –20 –5 10 25 40 55 70 85 100
–50 –35 –20 –5 10 25 40 55 70 85 100
4.5
6
7.5
9
15
10.5 12 13.5
(V)
TEMPERATURE (°C)
V
TEMPERATURE (°C)
PWR
2978 G25
2978 G27
2978 G26
2978fc
12
LTC2978
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT_EN[3:0] and VIN_EN Output
High Voltage vs Load Current
Supply Current vs Supply Voltage
Supply Current vs Temperature
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
10.5
10.4
10.3
10.2
10.1
10.0
9.9
10.16
10.14
V
= V
DD33
V
= 12V
PWR
PWR
85°C
25°C
10.12
–40°C
10.10
10.08
10.06
10.04
9.8
9.5
10.02
3.1
3.2
3.4
3
3.5
3.6
3.3
0
1
2
3
7
4
5
6
–50
–5
25 40 55 70 85 100
–35 –20
10
CURRENT SOURCING (µA)
V
(V)
TEMPERATURE (°C)
DD33
2978 G28
2978 G30
2978 G29
V
OUT_EN[3:0] and VIN_EN VOL
DAC Output Impedance vs
Frequency
VOUT_EN[7:4] VOL vs Current
vs Current
1000
100
10
0.6
0.5
0.4
0.3
0.2
0.1
0
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
85°C
85°C
25°C
25°C
1
–40°C
–40°C
0.1
0.01
0.01
0.1
1
10
100
1000
0
8
12
(mA)
16
20
24
8
12
4
0
2
4
6
(mA)
10
I
FREQUENCY (kHz)
I
SINK
SINK
2978 G31
2978 G33
2978 G32
PWRGD and FAULTBzn VOL
vs Current
ALERTB VOL vs Current
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.2
1.0
0.8
0.6
0.4
0.2
0
85°C
25°C
–40°C
85°C
25°C
–40°C
8
12
0
2
4
6
10
0
4
6
8
10
12
2
I
(mA)
I
(mA)
SINK
SINK
2978 G35
2978 G34
2978fc
13
LTC2978
PIN FUNCTIONS
PIN NAME
PIN NUMBER
PIN TYPE
In
DESCRIPTION
V
V
V
V
V
V
V
V
V
V
V
V
1*
2*
3*
4
ꢀ
6
7
8
9
1±
11
12
13
14
DC/DC Converter Differential (–) Output Voltage-6 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-7 Sensing Pin
DC/DC Converter Differential (–) Output Voltage or Current-7 Sensing Pin
DC/DC Converter Enable-± Pin. Output High Voltage Optionally Pulled Up to 12V by ꢀµA
DC/DC Converter Enable-1 Pin. Output High Voltage Optionally Pulled Up to 12V by ꢀµA
DC/DC Converter Enable-2 Pin. Output High Voltage Optionally Pulled Up to 12V by ꢀµA
DC/DC Converter Enable-3 Pin. Output High Voltage Optionally Pulled Up to 12V by ꢀµA
DC/DC Converter Open-Drain Pull-Down Output-4
DC/DC Converter Open-Drain Pull-Down Output-ꢀ
DC/DC Converter Open-Drain Pull-Down Output-6
DC/DC Converter Open-Drain Pull-Down Output-7
DC/DC Converter V ENABLE Pin. Output High Voltage Optionally Pulled Up to 12V by ꢀµA
SENSEM6
SENSEP7
SENSEM7
OUT_EN±
OUT_EN1
OUT_EN2
OUT_EN3
OUT_EN4
OUT_ENꢀ
OUT_EN6
OUT_EN7
IN_EN
In
In
Out
Out
Out
Out
Out
Out
Out
Out
±ut
IN
DNC
Do Not Connect Do Not Connect to This Pin
V
In
V SENSE Input. This Voltage is Compared Against the V On and Off Voltage Thresholds in Order to
IN IN
Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters
IN_SNS
V
1ꢀ
16
In
V
Serves as the Unregulated Power Supply Input to the Chip (4.ꢀV to 1ꢀV). If a 4.ꢀV to 1ꢀV Supply
PWR
PWR
Voltage is Unavailable, Short V
GND with ±.1µF Capacitor.
to V
and Power the Chip Directly from a 3.3V Supply. Bypass to
PWR
DD33
V
In/Out
If Shorted to V
, it Serves as 3.13V to 3.47V Supply Input Pin. Otherwise it is a 3.3V Internally
PWR
DD33
Regulated Voltage Output (Use 1±±nF Decoupling Capacitor to GND)
Input for Internal 2.ꢀV Sub-Regulator. Short This Pin to Pin 16
2.ꢀV Internally Regulated Voltage Output. Bypass to GND with a ±.1µF Capacitor
Digital Input. Write-Protect Input Pin, Active High
Power Good Open-Drain Output. Indicates When Outputs are Power Good. Can be Used as System
Power-On Reset. The Latency of This Signal May Be as Long as the ADC Latency. See Note 6.
V
V
WP
17
18
19
2±
In
In/Out
In
DD33
DD2ꢀ
PWRGD
Out
SHARE_CLK
WDI/RESETB
21
22
In/Out
In
Bidirectional Clock Sharing Pin. Connect a ꢀ.49k Pull-Up Resistor to V
DD33
Watchdog Timer Interrupt and Chip Reset Input. Connect a 1±k Pull-Up Resistor to V
. Rising Edge
DD33
Resets Watchdog Counter. Holding This Pin Low for More Than t
Resets the Chip
RESETB
FAULTB±±
FAULTB±1
FAULTB1±
FAULTB11
23
24
2ꢀ
26
In/Out
In/Out
In/Out
In/Out
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-±±. Connect a 1±k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-±1. Connect a 1±k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-1±. Connect a 1±k Pull-Up
Resistor to V
DD33
Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-11. Connect a 1±k Pull-Up
Resistor to V
DD33
SDA
SCL
27
28
29
3±
31
32
33
34
3ꢀ
36*
37*
38
39
4±
In/Out
In
Out
In
In
In
PMBus Bidirectional Serial Data Pin
PMBus Serial Clock Input Pin (4±±kHz Maximum)
Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation
Control Pin ± Input
Control Pin 1 Input
Ternary Address Select Pin ± Input. Connect to V
Ternary Address Select Pin 1 Input. Connect to V
Reference Voltage Output. Needs ±.1µF Decoupling Capacitor to REFM
Reference Return Pin. Needs ±.1µF Decoupling Capacitor to REFP.
DC/DC Converter Differential (+) Output Voltage-± Sensing Pin
DC/DC Converter Differential (–) Output Voltage-± Sensing Pin
DAC± Return. Connect to Channel ± DC/DC Converter’s GND Sense or Return to GND
DAC± Output
ALERTB
CONTROL±
CONTROL1
ASEL±
ASEL1
REFP
, GND or Float to Encode 1 of 3 Logic States
, GND or Float to Encode 1 of 3 Logic States
DD33
In
DD33
Out
Out
In
REFM
V
V
V
V
V
SENSEP±
SENSEM±
DACM±
DACP±
In
Out
Out
Out
DAC1 Output
DACP1
2978fc
14
LTC2978
PIN FUNCTIONS
PIN NAME
PIN NUMBER
PIN TYPE
Out
In
DESCRIPTION
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
41
DAC1 Return. Connect to Channel 1 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage or Current-1 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-1 Sensing Pins
DAC2 Output
DAC2 Return. Connect to Channel 2 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-2 Sensing Pin
DC/DC Converter Differential (+) Output Voltage or Current-3 Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-3 Sensing Pins
DAC3 Output
DAC3 Return. Connect to Channel 3 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage-4 Sensing Pin
DC/DC Converter Differential (–) Output Voltage-4 Sensing Pin
DAC4 Return. Connect to Channel 4 DC/DC Converter’s GND Sense or Return to GND
DAC4 Output
DACM1
42*
43*
44
SENSEP1
SENSEM1
DACP2
In
Out
Out
In
In
In
4ꢀ
DACM2
46*
47*
48*
49*
ꢀ±
SENSEP2
SENSEM2
SENSEP3
SENSEM3
DACP3
In
Out
Out
In
ꢀ1
DACM3
ꢀ2*
ꢀ3*
ꢀ4
ꢀꢀ
ꢀ6
ꢀ7
ꢀ8
ꢀ9
6±
SENSEP4
SENSEM4
DACM4
In
Out
Out
Out
Out
Out
Out
Out
Out
In
DACP4
DACꢀ Output
DACPꢀ
DACꢀ Return. Connect to Channel ꢀ DC/DC Converter’s GND Sense or Return to GND
DAC6 Return. Connect to Channel 6 DC/DC Converter’s GND Sense or Return to GND
DAC6 Output
DACMꢀ
DACM6
DACP6
DAC7 Output
DACP7
61
DAC7 Return. Connect to Channel 7 DC/DC Converter’s GND Sense or Return to GND
DC/DC Converter Differential (+) Output Voltage or Current-ꢀ Sensing Pins
DC/DC Converter Differential (–) Output Voltage or Current-ꢀ Sensing Pins
DC/DC Converter Differential (+) Output Voltage-6 Sensing Pin
Exposed Pad, Must be Soldered to PCB
DACM7
62*
63*
64*
6ꢀ
SENSEPꢀ
SENSEMꢀ
SENSEP6
In
In
Ground
GND
*Any unused V
or V
or V pins must be tied to GND.
DACMn
SENSEPn
SENSEMn
2978fc
15
LTC2978
BLOCK DIAGRAM
3.3V REGULATOR
IN
V
15
16
V
V
OUT
PWR
V
DD
V
DD33
2.5V REGULATOR
IN
OUT
V
V
17
18
V
V
DD33
DD25
3R
V
V
SENSEM0
SENSEP0
V
14
IN_SNS
R
V
V
SENSEM1
36
37
42
43
46
47
48
49
52
53
62
63
64
1
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
SENSEP0
SENSEM0
SENSEP1
SENSEM1
SENSEP2
SENSEM2
SENSEP3
SENSEM3
SENSEP4
SENSEM4
SENSEP5
SENSEM5
SENSEP6
SENSEM6
SENSEP7
SENSEM7
SENSEP1
GND 65
V
V
SENSEM2
SENSEP2
V
V
SENSEM3
SENSEP3
–
+
–
+
V
V
SENSEM4
SENSEP4
INTERNAL
TEMP
SENSOR
CMP0
MUX
+
–
10-BIT
VDAC
V
V
SENSEM5
SENSEP5
V
V
SENSEM6
SENSEP6
V
V
SENSEM7
SENSEP7
+
–
16-BIT
+
∆∑ ADC
2
SC
CMP0
3
–
DAC0
10 BITS
+
ADC
CLOCKS
39
40
44
50
55
56
59
60
V
V
V
V
V
V
V
V
VBUF0
DACP0
DACP1
DACP2
DACP3
DACP4
DACP5
DACP6
DACP7
–
V
DD
REFERENCE
1.232V
REFP 34
REFM 35
(TYP)
38
41
45
51
54
57
58
61
V
V
V
V
V
V
V
V
DACM0
DACM1
DACM2
DACM3
DACM4
DACM5
DACM6
DACM7
NONVOLATILE MEMORY
EEPROM
SCL 28
SDA 27
PMBus
INTERFACE
ALERTB 29
ASEL0 32
ASEL1 33
2
(400kHz I C
RAM
COMPATIBLE)
ADC_RESULTS
MONITOR LIMITS
SERVO TARGETS
WP 19
4
5
6
7
V
V
V
V
OUT_EN0
OUT_EN1
OUT_EN2
OUT_EN3
OUTPUT
CONFIG
CONTROL0 30
CONTROL1 31
WDI/RESETB 22
FAULTB00 23
FAULTB01 24
FAULTB10 25
FAULTB11 26
CLOCK
GENERATION
OSCILLATOR
CONTROLLER
PMBus ALGORITHM
FAULT PROCESSOR
WATCHDOG
12
V
IN_EN
V
DD
8
9
V
V
V
V
OUT_EN4
OUT_EN5
OUT_EN6
OUT_EN7
SEQUENCER
UVLO
OPEN-DRAIN
OUTPUT
10
11
PWRGD
20
SHARE_CLK 21
2978 BD
2978fc
16
LTC2978
OPERATION
OPERATION OVERVIEW
n
n
Restore EEPROM contents through PMBus program-
ming or when V
is applied on power-up.
DD33
The LTC2978 is a PMBus programmable power supply
controller, monitor, sequencer and voltage supervisor that
can perform the following operations:
Report the DC/DC converter output voltage status
through the PMBus interface and the power good
output.
n
Accept PMBus compatible programming commands.
n
n
Generate interrupt requests by asserting the ALERTB
pin in response to supported PMBus faults and
warnings.
n
Provide DC/DC converter input voltage and output volt-
age/current read back through the PMBus interface.
n
Control the output of DC/DC converters that set the
Coordinate system wide fault responses for all DC/DC
converters connected to the FAULTBz± and FAULTBz1
pins.
output voltage with a trim pin or DC/DC converters
that set the output voltage using an external resistor
feedback network.
n
n
n
Synchronizesequencingdelaysorshutdownformultiple
devices using the SHARE_CLK pin.
n
Sequence the start-up of DC/DC converters via PMBus
programming and the CONTROL input pins.
Software and hardware write protect the command
registers.
n
Trim the DC/DC converter output voltage (typically in
±.25 steps), in closed-loop servo operating mode,
through PMBus programming.
Disable the input voltage to the supervised DC/DC
converters in response to output voltage OV and UV
faults.
n
Margin the DC/DC converter output voltage to PMBus
programmed limits.
n
n
Log telemetry and status data to EEPROM in response
to a faulted-off condition
n
Allow the user to trim or margin the DC/DC converter
outputvoltageinamanualoperatingmodebyproviding
direct access to the margin DAC.
Supervise an external microcontroller’s activity for a
stalled condition with a programmable watchdog timer
and reset it if necessary.
n
Supervise the DC/DC converter output voltage, input
voltage, and the LTC2978 die temperature for over-
value/undervalue conditions with respect to PMBus
programmedlimitsandgenerateappropriatefaultsand
warnings.
n
Prevent a DC/DC converter from re-entering the ON
state after a power cycle until a programmable interval
(MFR_RESTART_DELAY) has elapsed and its output
has decayed below a programmable threshold voltage
(MFR_VOUT_DISCHARGE_THRESHOLD).
n
Respond to a fault condition by either continuing op-
eration indefinitely, latching off after a programmable
deglitchperiodorlatchingoffimmediately.Aretrymode
maybeusedtoautomaticallyrecoverfromalatched-off
condition.
n
Record minimum and maximum observed values of
input voltage, output voltages and temperature.
EEPROM
n
Optionally stop trimming the DC/DC converter output
The LTC2978 contains internal EEPROM (nonvolatile
memory) to store configuration settings and fault log
information. EEPROM endurance, retention, and mass
write operation time are specified over the operating tem-
peraturerange.SeeElectricalCharacteristicsandAbsolute
Maximum Ratings sections.
voltage after it reached the initial margin or nominal
target. Optionally allow servo to resume if target drifts
outside of V
warning limits.
OUT
n
StorecommandregistercontentswithCRCtoEEPROM
through PMBus programming.
2978fc
17
LTC2978
OPERATION
Nondestructive operation above T = 8ꢀ°C is possible
RESET
J
although the Electrical Characteristics are not guaranteed
and the EEPROM will be degraded.
Holding the WDI/RESETB pin low for more than t
RESETB
will cause the LTC2978 to enter the power-on reset state.
Followingthesubsequentrising-edgeoftheWDI/RESETB
pin, the LTC2978 will execute its power-on sequence per
the user configuration stored in EEPROM.
Operating the EEPROM above 8ꢀ°C may result in a deg-
radation of retention characteristics. The fault logging
function, which is useful in debugging system problems
that may occur at high temperatures, only writes to fault
log EEPROM locations. If occasional writes to these reg-
isters occur above 8ꢀ°C, a slight degradation in the data
retention characteristics of the fault log may occur.
WRITE-PROTECT PIN
The WP pin allows the user to write-protect the LTC2978’s
configuration registers. The WP pin is active high, and
when asserted it provides Level 2 protection: all writes
are disabled except to the WRITE_PROTECT, PAGE,
STORE_USER_ALL, OPERATION, MFR_PAGE_FF_MASK
and CLEAR_FAULTS commands. The most restrictive set-
ting between theWP pin and WRITE_PROTECTcommand
will override. For example if WP = 1 and WRITE_PROTECT
= ±x8±, then the WRITE_PROTECT command overrides,
since it is the most restrictive.
It is recommended that the EEPROM not be written using
STORE_USER_ALLorbulkprogrammingwhenT >8ꢀ°C.
J
The degradation in EEPROM retention for temperatures
>8ꢀ°C can be approximated by calculating the dimension-
less acceleration factor using the following equation.
Ea
k
1
1
•
−
TUSE +273 TSTRESS +273
AF = e
Where:
OTHER OPERATIONS
Clock Sharing
AF = acceleration factor
Ea = activation energy = 1.4 eV
Multiple LTC PMBus devices can synchronize their clocks
in an application by connecting together the open-drain
SHARE_CLK input/outputs to a pull-up resistor as a wired
OR. In this case the fastest clock will take over and syn-
chronize all LTC2978s.
−ꢀ
k = 8.62ꢀ×1± eV/°K
T
T
= 8ꢀ°C specified junction temperature
USE
= actual junction temperature °C
STRESS
SHARE_CLKcanoptionallybeusedtosynchronizeON/OFF
Example: Calculate the effect on retention when operating
at a junction temperature of 9ꢀ°C for 1± hours.
dependency on V across multiple chips by setting bit 3
IN
(Mfr_config_all_vin_share_enable)oftheMFR_CONFIG_
ALL register. When configured this way the chip will hold
SHARE_CLK low when the unit is off for insufficient input
voltage and upon detecting that SHARE_CLK is held low
the chip will disable all channels after a brief deglitch
period. When the SHARE_CLK pin is allowed to rise, the
chip will respond by beginning a soft-start requence. In
this case the slowest VIN_ON detection will take over and
synchronize other chips to its soft-start sequence.
T
T
= 9ꢀ°C
STRESS
= 8ꢀ°C
USE
AF = 3.4
Equivalent operating time at 8ꢀ°C = 34 hours.
So the overall retention of the EEPROM was degraded by
34 hours as a result of operation at a junction temperature
of 9ꢀ°C for 1± hours. Note that the effect of this overstress
is negligible when compared to the overall EEPROM
retention rating of 87,6±± hours at a maximum junction
temperature of 8ꢀ°C.
2978fc
18
LTC2978
OPERATION
PMBus SERIAL DIGITAL INTERFACE
The PMBus two wire interface is an incremental extension
2
of the SMBus. SMBus is built upon I C with some minor
TheLTC2978communicateswithahost(master)usingthe
standard PMBus serial bus interface. The PMBus Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
differences in timing, DC parameters and protocol. The
2
SMBus protocols are more robust than simple I C byte
commands because they provide timeouts to prevent
bus hangs and optional packet error checking (PEC) to
ensure data integrity. In general, a master device that
2
can be configured for I C communication can be used
TheLTC2978isaslavedevice.Themastercancommunicate
with the LTC2978 using the following formats:
for PMBus communication with little or no change to
hardware or firmware.
n
Master transmitter, slave receiver
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification
Part 1 Revision 1.1: paragraph ꢀ: Transport. This can be
found at:
n
Master receiver, slave transmitter
The following SMBus protocols are supported:
n
Write Byte, Write Word, Send Byte
www.pmbus.org.
n
Read Byte, Read Word, Block Read
For a description of the differences between SMBus and
2
n
I C, refer to system management bus (SMBus) specifica-
Alert Response Address
tionversion2.±:AppendixB–DifferencesBetweenSMBus
Figures 1-12 illustrate the aforementioned SMBus pro-
tocols. All transactions support PEC (parity error check)
and GCP (group command protocol). The Block Read
supports 2ꢀꢀ bytes of returned data. For this reason, the
PMBustimeoutmaybeextendedusingtheMfr_config_all_
longer_pmbus_timeout setting.
2
and I C. This can be found at:
www.smbus.org.
2
When using an I C controller to communicate with a
PMBus part it is important that the controller be able to
write a byte of data without generating a stop. This will
allow the controller to properly form the repeated start
of the PMBus read command by concatenating a start
The LTC2978 will not acknowledge any PMBus command
if it is still busy with a STORE_USER_ALL, RESTORE_
USER_ALL, MFR_CONFIG_LTC2978 or if fault log data
is being written to the EEPROM. Status_word_busy will
also be set.
2
command byte write with an I C read.
PMBus
PMBus is an industry standard that defines a means
of communication with power conversion devices. It is
comprised of an industry standard SMBus serial interface
and the PMBus command language.
2978fc
19
LTC2978
OPERATION
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
x
COMMAND CODE
A
x
P
S
Sr
START CONDITION
REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
x
SHOWN UNDER A FIELD INDICATES THAT THE
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A
ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P
STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
CONTINUATION OF PROTOCOL
...
2978 F01a
Figure 1a. PMBus Packet Protocol Diagram Element Key
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
P
2978 F01b
Figure 1b. Write Byte Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
2978 F02
Figure 2. Write Word Protocol
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE
A
PEC
A
P
2978 F03
Figure 3. Write Byte Protocol with PEC
1
7
1
1
8
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
2978 F04
Figure 4. Write Word Protocol with PEC
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
P
2978 F05
Figure 5. Send Byte Protocol
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
PEC
A
P
2978 F06
Figure 6. Send Byte Protocol with PEC
2978fc
20
LTC2978
OPERATION
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
S
SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
P
1 2978 F07
Figure 7. Read Word Protocol
1
7
1
1
8
1
1
7
1
1
8
1
8
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
S
SLAVE ADDRESS Rd
A
DATA BYTE LOW
A
DATA BYTE HIGH
A
PEC
A
P
1 2978 F08
Figure 8. Read Word Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
S
SLAVE ADDRESS Rd
A
DATA BYTE
A
P
1 2978 F09
Figure 9. Read Byte Protocol
1
7
1
1
8
1
1
7
1
1
8
1
1
1
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
S
SLAVE ADDRESS Rd
A
DATA BYTE
A
PEC
A
P
2978 F10
Figure 10. Read Byte Protocol with PEC
1
7
1
1
8
1
1
7
1
1
8
1
...
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr
A
BYTE COUNT = N
A
2978 F11
SLAVE ADDRESS Rd
...
...
8
1
8
1
8
1
A
1
1
DATA BYTE 1
A
DATA BYTE 2
A
DATA BYTE N
P
Figure 11. Block Read
1
7
1
1
8
1
1
7
1
1
8
1
...
S
SLAVE ADDRESS Wr
A
COMMAND CODE
A
Sr
A
BYTE COUNT = N
A
2978 F12
SLAVE ADDRESS Rd
...
...
8
1
8
1
8
1
8
1
A
1
1
DATA BYTE 1
A
DATA BYTE 2
A
A
P
DATA BYTE N
PEC
Figure 12. Block Read with PEC
2978fc
21
LTC2978
OPERATION
Device Address
changed unless the desired range of addresses overlap
existingaddresses. Watchthattheaddressrangedoesnot
2
The I C/SMBus address of the LTC2978 equals the base
2
overlap with other I C/SMBus device or global addresses,
address + N where N is a number from ± to 8. N can be
2
including I C/SMBus multiplexers and bus buffers. This
configuredbysettingtheASEL±andASEL1pinstoV
,
DD33
will bring you great happiness.
GNDorFLOAT.SeeTable1.Usingonebaseaddressandthe
ninevaluesofN,nineLTC2978scanbeconnectedtogether
to control 72 outputs. The base address is stored in the
MFR_I2C_BASE_ADDRESS register. The base address
can be written to any value, but generally should not be
TheLTC2978alwaysrespondstoitsglobaladdressandthe
SMBus Alert Response address regardless of the state of
itsASELpinsandtheMFR_I2C_BASE_ADDRESSregister.
Table 1. LTC2978 Device Address Look-Up Table
ADDRESS
DESCRIPTION
HEX DEVICE
ADDRESS
BINARY DEVICE ADDRESS BITS
ADDRESS PINS
7-Bit
±C
8-Bit
19
6
±
1
1
1
1
1
1
1
1
1
1
ꢀ
±
±
±
±
±
±
1
1
1
1
1
4
±
1
1
1
1
1
±
±
±
±
±
3
1
1
1
1
1
1
±
±
±
±
±
2
1
±
1
1
1
1
±
±
±
±
1
1
±
1
±
±
1
1
±
±
1
1
±
±
±
1
±
1
±
1
±
1
±
1
±
R/W
1
ASEL1
ASEL±
Alert Response
Global
N = ±
X
X
X
X
ꢀB
ꢀC*
ꢀD
ꢀE
ꢀF
B6
B8
BA
BC
BE
C±
C2
C4
C6
C8
±
±
L
L
N = 1
±
L
NC
H
N = 2
±
L
N = 3
±
NC
NC
NC
H
L
N = 4
6±
61
62
63
64
±
NC
H
N = ꢀ
±
N = 6
±
L
N = 7
±
H
NC
H
N = 8
±
H
H = Tie to V
, NC = No Connect = Open or Float, L = Tie to GND, X = Don’t Care
DD33
*MFR_I2C_BASE_ADDRESS = 7bit ꢀC (Factory Default)
2978fc
22
LTC2978
OPERATION
Processing Commands
The LTC2978 uses a dedicated processing block to ensure quick response to all of its commands. There are a few
exceptions where the part will NACK a subsequent command because it is still processing the previous command.
These are summarized in the following tables.
EEPROM Related Commands
COMMAND
TYPICAL DELAY*
COMMENT
STORE_USER_ALL
Mass_write
See Electrical Characterization table. The LTC2978 will not accept any commands while it is
transferring register contents to the EEPROM. The command byte will be NACKed.
RESTORE_USER_ALL
MFR_DATA_LOG_CLEAR
MFR_DATA_LOG_STORE
Internal Fault log
3±ms
17ꢀms
2±ms
1±ms
The LTC2978 will not accept any commands while it is transferring EEPROM data to command
registers. The command byte will be NACKed.
The LTC2978 will not accept any commands while it is initializing the fault log EEPROM space. The
command byte will be NACKed.
The LTC2978 will not accept any commands while it is transferring the fault log RAM buffer to
EEPROM space. The command byte will be NACKed.
An internal fault log event is a one time event that uploads the contents of the fault log to EEPROM in
response to a fault. Internal fault logging may be disabled. Commands received during this EEPROM
write are NACKed.
MFR_DATA_LOG_
RESTORE
2ms
The LTC2978 will not accept any commands while it is transferring EEPROM data to the fault log RAM
buffer. The command byte will be NACKed.
*The typical delay is measured from the command’s stop to the next command’s start.
COMMAND
TYPICAL DELAY*
COMMENT
MFR_CONFIG_LTC2978
<ꢀ±µs
The LTC2978 will not accept any commands while it is completing this command. The command byte
will be NACKed.
*The delay is measured from the command’s stop to the next command’s start.
Other PMBus Timing Notes
COMMAND
COMMENT
CLEAR_FAULTS
The LTC2978 will accept commands while it is completing this command but the affected status flags will not be cleared for
up to ꢀ±±µs.
2978fc
23
LTC2978
PMBus COMMAND SUMMARY
Summary Table
DEFAULT
VALUE
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
PAGE
±x±± Channel or page currently selected for any R/W Byte
command that supports paging.
N
Y
Y
Reg
Reg
Reg
±x±±
±x±±
±x12
29
3±
31
OPERATION
±x±1 Operating mode control. On/Off, Margin
High and Margin Low.
R/W Byte
R/W Byte
Send Byte
Y
Y
ON_OFF_CONFIG
±x±2 CONTROL pin & PMBus bus on/off
command setting.
CLEAR_FAULTS
±x±3 Clear any fault bits that have been set.
Y
N
NA
31
32
WRITE_PROTECT
±x1± Level of protection provided by the device R/W Byte
against accidental changes.
Reg
Y
±x±±
STORE_USER_ALL
RESTORE_USER_ALL
CAPABILITY
±x1ꢀ Store entire operating memory to
EEPROM.
Send Byte
Send Byte
R Byte
N
N
N
NA
NA
32
32
32
±x16 Restore entire operating memory from
EEPROM.
±x19 Summary of PMBus optional
communication protocols supported by
this device.
Reg
±xE±
VOUT_MODE
VOUT_COMMAND
VOUT_MAX
±x2± Output voltage data format and mantissa
R Byte
Y
Y
Y
Reg
L16
L16
±x13
33
33
33
–13
exponent. (2
)
±x21 Servo Target. Nominal DC/DC converter
output voltage setpoint.
R/W Word
V
V
Y
Y
1.±
±x2±±±
±x24 Upper limit on the output voltage the unit R/W Word
can command regardless of any other
commands.
4.±
±x8±±±
VOUT_MARGIN_HIGH
VOUT_MARGIN_LOW
VIN_ON
±x2ꢀ Margin high DC/DC converter output
voltage setting.
R/W Word
R/W Word
R/W Word
R/W Word
Y
Y
N
N
L16
L16
L11
L11
V
V
V
V
Y
Y
Y
Y
1.±ꢀ
33
33
33
33
±x219A
±x26 Margin low DC/DC converter output
voltage setting.
±.9ꢀ
±x1E66
±x3ꢀ Input voltage above which power
conversion can be enabled.
1±.±
±xD28±
VIN_OFF
±x36 Input voltage below which power
9.±
±xD24±
conversion is disabled. All V
go off immediately.
pins
OUT_EN
VOUT_OV_FAULT_LIMIT
±x4± Output overvoltage fault limit
R/W Word
R/W Byte
R/W Word
R/W Word
R/W Word
Y
Y
Y
Y
Y
L16
Reg
L16
L16
L16
V
Y
Y
Y
Y
Y
1.1
33
3ꢀ
33
33
33
±x2333
VOUT_OV_FAULT_
RESPONSE
±x41 Action to be taken by the device when an
output overvoltage fault is detected.
±x8±
VOUT_OV_WARN_LIMIT
VOUT_UV_WARN_LIMIT
VOUT_UV_FAULT_LIMIT
±x42 Output overvoltage warning limit .
V
V
V
1.±7ꢀ
±x2266
±x43 Output undervoltage warning limit
±.92ꢀ
±x1D9A
±x44 Output undervoltage fault limit. Limit
used to determine if TON_MAX_FAULT
has been met and the unit is on.
±.9
±x1CCD
VOUT_UV_FAULT_
RESPONSE
±x4ꢀ Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte
Y
N
Reg
L11
Y
Y
±x7F
3ꢀ
34
OT_FAULT_LIMIT
±x4F Overtemperature fault limit setting.
R/W Word
°C
8ꢀ.±
±xEAA8
2978fc
24
LTC2978
PMBus COMMAND SUMMARY
Summary Table
DEFAULT
VALUE
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
OT_FAULT_RESPONSE
±xꢀ± Action to be taken by the device when an
overtemperature fault is detected.
R/W Byte
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Reg
L11
L11
L11
Reg
L11
Reg
L11
L11
L11
Reg
L16
L16
L11
Y
±xB8
36
34
34
34
36
33
36
33
33
33
36
33
33
34
OT_WARN_LIMIT
±xꢀ1 Overtemperature warning limit setting.
±xꢀ2 Undertemperature warning limit.
±xꢀ3 Undertemperature fault limit.
R/W Word
R/W Word
R/W Word
R/W Byte
°C
°C
°C
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
7ꢀ.±
±xEAꢀ8
UT_WARN_LIMIT
±
±x8±±±
UT_FAULT_LIMIT
–ꢀ.±
±xCD8±
UT_FAULT_RESPONSE
VIN_OV_FAULT_LIMIT
±xꢀ4 Action to be taken by the device when an
undertemperature fault is detected.
±xB8
±xꢀꢀ Input overvoltage fault limit measured at R/W Word
pin
V
1ꢀ.±
±xD3C±
V
IN_SNS
VIN_OV_FAULT_RESPONSE ±xꢀ6 Action to be taken by the device when an
input overvoltage fault is detected.
R/W Byte
±x8±
VIN_OV_WARN_LIMIT
VIN_UV_WARN_LIMIT
VIN_UV_FAULT_LIMIT
±xꢀ7 Input overvoltage warning limit measured R/W Word
at V pin
V
V
V
14.±
±xD38±
IN_SNS
±xꢀ8 Input undervoltage warning limit
measured at V pin.
R/W Word
±
±x8±±±
IN_SNS
±xꢀ9 Input undervoltage fault limit measured at R/W Word
pin
±
V
±x8±±±
IN_SNS
VIN_UV_FAULT_RESPONSE ±xꢀA Action to be taken by the device when an
input undervoltage fault is detected.
R/W Byte
±x±±
POWER_GOOD_ON
POWER_GOOD_OFF
TON_DELAY
±xꢀE Output voltage at or above which a power R/W Word
V
V
±.96
±x1EB8
good should be asserted.
±xꢀF Output voltage at or below which a power R/W Word
good should be deasserted.
±.94
±x1E14
±x6± Time from CONTROL pin and/or
OPERATION command = ON to V
pin = ON.
R/W Word
ms
1.±
±xBA±±
OUT_EN
TON_RISE
±x61 Time from when the output starts to rise
until the LTC2978 optionally soft-connects
its DAC and begins to servo the output
voltage to the desired value.
R/W Word
Y
Y
L11
L11
ms
ms
Y
Y
1±.±
34
34
±xD28±
TON_MAX_FAULT_LIMIT
±x62 Maximum time from V
= ON
R/W Word
1ꢀ.±
±xD3C±
OUT_EN
assertion that an UV condition will be
tolerated before a TON_MAX_FAULT
condition results.
TON_MAX_FAULT_
RESPONSE
±x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
R/W Byte
Y
Y
Reg
L11
Y
Y
±xB8
36
34
TOFF_DELAY
±x64 Time from CONTROL pin and/or
R/W Word
ms
1.±
±xBA±±
OPERATION command = OFF to V
pin = OFF.
OUT_EN
STATUS_BYTE
STATUS_WORD
STATUS_VOUT
±x78 One byte summary of the unit's fault
condition.
R Byte
R Word
R Byte
Y
Y
Y
Reg
Reg
Reg
NA
NA
NA
37
38
38
±x79 Two byte summary of the unit's fault
condition.
±x7A Output voltage fault and warning status.
2978fc
25
LTC2978
PMBus COMMAND SUMMARY
Summary Table
DEFAULT
VALUE
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
STATUS_INPUT
±x7C Input voltage fault and warning status
measured at VIN_SNS pin.
R Byte
N
N
N
Y
Reg
Reg
Reg
Reg
NA
NA
NA
NA
39
39
4±
4±
STATUS_TEMPERATURE
STATUS_CML
±x7D Temperature fault and warning status for
READ_TEMPERATURE_1.
R Byte
R Byte
R Byte
±x7E Communication and memory fault and
warning status.
STATUS_MFR_SPECIFIC
±x8± Manufacturer specific fault and state
information.
READ_VIN
±x88 Input voltage measured at VIN_SNS pin..
±x8B DC/DC converter output voltage.
±x8D Internal junction temperature.
R Word
R Word
R Word
R Byte
N
Y
N
N
L11
L16
L11
Reg
V
V
NA
NA
41
41
41
41
READ_VOUT
READ_TEMPERATURE_1
PMBUS_REVISION
°C
NA
±x98 PMBus revision supported by this device.
Current revision is 1.1.
±x11
MFR_CONFIG_LTC2978
±xD± Configuration bits that are channel
specific.
R/W Word
Y
N
Y
Reg
Reg
Reg
Y
Y
Y
±x±±8±
±x7B
42
43
44
MFR_CONFIG_ALL_
LTC2978
±xD1 Configuration bits that are common to all R/W Byte
pages.
MFR_FAULTBz±_
PROPAGATE
±xD2 Configuration that determines if a
channel’s faulted off state is propagated
to the FAULTB±± and FAULTB1± pins.
R/W Byte
±x±±
MFR_FAULTBz1_
PROPAGATE
±xD3 Manufacturer configuration that
Configuration that determines if a
R/W Byte
Y
Reg
Y
±x±±
44
channel’s faulted off state is propagated
to the FAULTB±1 and FAULTB11 pins.
MFR_PWRGD_EN
±xD4 Configuration for mapping PWRGD and
WDI/RESETB status to the PWRGD pin.
R/W Word
N
N
N
N
N
N
N
N
N
Y
N
Reg
Reg
Reg
Reg
Reg
Reg
Reg
L11
L11
L16
L11
Y
Y
Y
Y
Y
Y
Y
Y
Y
±x±±±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
4ꢀ
46
46
46
46
47
48
48
49
49
49
MFR_FAULTB±±_
RESPONSE
±xDꢀ Action to be taken by the device when the R/W Byte
FAULTB±± pin is asserted low.
MFR_FAULTB±1_
RESPONSE
±xD6 Action to be taken by the device when the R/W Byte
FAULTB±1 pin is asserted low.
MFR_FAULTB1±_
RESPONSE
±xD7 Action to be taken by the device when the R/W Byte
FAULTB1± pin is asserted low.
MFR_FAULTB11_
RESPONSE
±xD8 Action to be taken by the device when the R/W Byte
FAULTB11 pin is asserted low.
MFR_VINEN_OV_FAULT_
RESPONSE
±xD9 Action to be taken by the V
pin in
R/W Byte
R/W Byte
R/W Word
R/W Word
R Word
IN_EN
response to a VOUT_OV_FAULT
MFR_VINEN_UV_FAULT_
RESPONSE
±xDA Action to be taken by the V
pin in
IN_EN
response to a VOUT_UV_FAULT
MFR_RETRY_DELAY
MFR_RESTART_DELAY
MFR_VOUT_PEAK
MFR_VIN_PEAK
±xDB Retry interval during FAULT retry mode.
ms
ms
V
2±±.±
±xF32±
±xDC Delay from actual CONTROL active edge
to virtual CONTROL active edge.
4±±.±
±xFB2±
±xDD Maximum measured value of READ_
VOUT.
NA
±xDE Maximum measured value of READ_VIN.
R Word
V
NA
2978fc
26
LTC2978
PMBus COMMAND SUMMARY
Summary Table
DEFAULT
VALUE
FLOAT
HEX
CMD
DATA
REF
PAGE
COMMAND NAME
CODE DESCRIPTION
TYPE
PAGED FORMAT UNITS
NVM
MFR_TEMPERATURE_
PEAK
±xDF Maximum measured value of READ_
TEMPERATURE_1.
R Word
N
Y
N
N
N
N
L11
U16
L11
L11
L11
Reg
°C
NA
49
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ1
MFR_DAC
±xE± Manufacturer register that contains the
code of the 1±-bit DAC.
R/W Word
R/W Word
R/W Word
R/W Word
R/W Byte
Y
Y
Y
Y
Y
±x±±±±
MFR_POWERGOOD_
ASSERTION_DELAY
±xE1 Power good output assertion delay.
ms
ms
ms
1±±.±
±xEB2±
MFR_WATCHDOG_T_FIRST ±xE2 First watchdog timer interval.
±
±x8±±±
MFR_WATCHDOG_T
MFR_PAGE_FF_MASK
±xE3 Watchdog timer interval.
±
±x8±±±
±xE4 Configuration defining which channels
respond to global page commands
(PAGE=±xFF).
±xFF
MFR_PADS
±xEꢀ Current state of selected digital I/O pads.
R Word
N
N
Reg
U16
N/A
ꢀ2
ꢀ2
2
MFR_I2C_BASE_ADDRESS ±xE6 Base value of the I C/SMBus address
byte.
R/W Byte
Y
Y
Y
±xꢀC
MFR_SPECIAL_ID
±xE7 Manufacturer code for identifying the
LTC2978
R Word
R Byte
N
Y
Reg
Reg
±x±121
ꢀ2
ꢀ3
MFR_SPECIAL_LOT
±xE8 Customer dependent codes that
identify the factory programmed user
configuration stored in EEPROM. Contact
factory for default value.
MFR_VOUT_DISCHARGE_
THRESHOLD
±xE9 Coefficient used to multiply VOUT_
R/W Word
Y
N
N
N
L11
Y
2.±
ꢀ3
ꢀꢀ
ꢀꢀ
ꢀꢀ
COMMAND in order to determine V
threshold voltage.
off
±xC2±±
OUT
MFR_FAULT_LOG_STORE
±xEA Command a transfer of the fault log from Send Byte
RAM to EEPROM. This causes the part to
NA
NA
NA
behave as if a channel has faulted off.
MFR_FAULT_LOG_
RESTORE
±xEB Command a transfer of the fault log
previously stored in EEPROM back to
RAM.
Send Byte
Send Byte
MFR_FAULT_LOG_CLEAR
±xEC Initialize the EEPROM block reserved for
fault logging and clear any previous fault
logging locks.
MFR_FAULT_LOG_STATUS ±xED Fault logging status.
R Byte
N
N
Reg
Reg
Y
Y
NA
NA
ꢀꢀ
ꢀ6
MFR_FAULT_LOG
±xEE Fault log data bytes. This sequentially
R Block
retrieved data is used to assemble a
complete fault log. 2ꢀ6 Bytes.
MFR_COMMON
±xEF Manufacturer status bits that are common
across multiple LTC chips.
R Byte
N
Reg
NA
ꢀ3
MFR_SPARE_±
MFR_SPARE_2
MFR_VOUT_MIN
MFR_VIN_MIN
±xF7 Scratchpad register
R/W Word
R/W Word
N
Y
Y
N
N
Reg
Reg
L16
L11
L11
Y
Y
±x±±±±
±x±±±±
NA
ꢀ3
ꢀ3
ꢀ4
ꢀ4
ꢀ4
±xF9 Paged scratchpad register
±xFB Minimum measured value of READ_VOUT. R Word
V
V
±xFC Minimum measured value of READ_VIN.
R Word
R Word
NA
MFR_TEMPERATURE_MIN ±xFD Minimum measured value of READ_
TEMPERATURE_1.
°C
NA
2978fc
27
LTC2978
PMBus COMMAND SUMMARY
Data Formats
L11
Linear_ꢀs_11s
PMBus data field b[1ꢀ:±]
N
Valueꢀ=ꢀYꢀ•ꢀ2
where N = b[1ꢀ:11] is a ꢀ-bit two’s complement integer and Y = b[1±:±] is an 11-bit two’s complement integer
Example:
READ_VIN = 1±V
For b[1ꢀ:±] = ±xD28± = 11±1_±±1±_1±±±_±±±±b
–6
ꢀ
Valueꢀ=ꢀ640ꢀ•ꢀ2 = 1±
See PMBus Spec Part II: Paragraph 7.1
L16
Linear_16u
PMBus data field b[1ꢀ:±]
N
Valueꢀ=ꢀYꢀ•ꢀ2 where Y = b[1ꢀ:±] is an unsigned integer and N = Vout_mode_parameter is a ꢀ-bit two’s complement
exponent that is hardwired to –13 decimal.
Example:
VOUT_COMMAND = 4.7ꢀV
For b[1ꢀ:±] = ±x98±± = 1±±1_1±±±_±±±±_±±±±b
–13
ꢀ
Valueꢀ=ꢀ38912ꢀ•ꢀ2 = 4.7ꢀ
See PMBus Spec Part II: Paragraph 8.3.1
Reg
U16
Register
PMBus data field b[1ꢀ:±] or b[7:±].
Bit field meaning is defined in detailed PMBus Command Register Description.
Integer Word
PMBus data field b[1ꢀ:±]
Value = Y where Y = b[1ꢀ:±] is a 16-bit unsigned integer
Example:
For b[1ꢀ:±] = ±x98±7 = 1±±1_1±±±_±±±±_±111b
Value = 38919
CF
Custom Format
PMBus data field b[1ꢀ:±]
Value is defined in detailed PMBus Command Register Description. This is often an unsigned or two’s complement
integer scaled by an MFR specific constant.
2978fc
28
LTC2978
PMBus COMMAND DESCRIPTION
OPERATION, MODE AND EEPROM COMMANDS
PAGE
The LTC2978 has eight pages that correspond to the eight DC/DC converter channels that can be managed. Each DC/DC
converter channel can be uniquely programmed by first setting the appropriate page.
The PAGE command provides the ability to configure, control and monitor multiple outputs on one unit.
Setting PAGE = ±xFF allows a simultaneous write to all pages for PMBus commands that support global page program-
ming. The only commands that support PAGE = ±xFF are OPERATION and ON_OFF_CONFIG. See MFR_PAGE_FF_MASK
for additional options. Reading any paged PMBus register with PAGE = ±xFF returns unpredictable data and will trigger
a CML fault.
PAGE Data Contents
BIT(S) SYMBOL PURPOSE
b[7:±] Page Page operation.
±x±±: All PMBus commands address channel/page ±.
±x±1: All PMBus commands address channel/page 1.
•
•
•
±x±7: All PMBus commands address channel/page 7.
±xXX: All nonspecified values reserved.
±xFF: A single PMBus write/send to commands that support this mode will simultaneously address all channels/pages with
MFR_PAGE_FF_MASK enabled.
2978fc
29
LTC2978
PMBus COMMAND DESCRIPTION
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the CONTROLn pin and ON_OFF_CON-
FIG. This command register responds to the global page command (PAGE=±xFF). The contents and functions of the
data byte are shown in the following tables.
OPERATION Data Contents (On_off_config_use_pmbus=1)
SYMBOL
BITS
Action
Operation_control[1:±] Operation_margin[1:±]
Operation_fault[1:±]
Reserved (read only)
b[7:6]
±±
b[ꢀ:4]
XX
b[3:2]
XX
b[1:±]
±±
Turn off immediately
Turn on
1±
±±
XX
±±
Margin Low (Ignore Faults and
Warnings)
1±
±1
±1
±±
Margin Low
1±
1±
±1
1±
1±
±1
±±
±±
Margin High (Ignore Faults and
Warnings
Margin High
1±
±1
1±
±±
1±
±±
±±
FUNCTION
Sequence off and margin to
nominal
XX
Sequence off and Margin Low
(Ignore Faults and Warnings)
±1
±1
±1
±±
Sequence off and Margin Low
±1
±1
±1
1±
1±
±1
±±
±±
Sequence off and Margin High
(Ignore Faults and Warnings)
Sequence off and Margin High
Reserved
±1
1±
1±
±±
All remaining combinations
OPERATION Data Contents (On_off_config_use_pmbus=0)
SYMBOL
BITS
Action
Operation_control[1:±] Operation_margin[1:±]
Operation_fault[1:±]
Reserved (read only)
b[7:6]
b[ꢀ:4]
±±
b[3:2]
XX
b[1:±]
±±
Output at Nominal
±±, ±1 or 1±
±±, ±1 or 1±
Margin Low (Ignore faults and
Warnings)
±1
±1
±±
Margin Low
±±, ±1 or 1±
±±, ±1 or 1±
±1
1±
1±
±1
±±
±±
FUNCTION
Margin High (Ignore Faults and
Warnings
Margin High
Reserved
±±, ±1 or 1±
1±
1±
±±
All remaining combinations
2978fc
30
LTC2978
PMBus COMMAND DESCRIPTION
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combination of CONTROLn pin input and PMBus bus commands
needed to turn the LTC2978 on/off, including the power-on behavior, as shown in the following table. This command
register responds to the global page command (PAGE=±xFF). After the part has initialized, an additional comparator
monitors VIN_SNS. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After
V is initially applied, the part will typically require 13ꢀms to initialize and begin the TON_DELAY timer. The readback
IN
of voltages and currents may require an additional 16±ms.
ON_OFF_CONFIG Data Contents
BITS(S) SYMBOL
OPERATION
b[7:ꢀ]
b[4]
Reserved
Don’t care. Always returns ±.
Controls default autonomous power-up operation.
On_off_config_controlled_on
±: Unit powers up regardless of the CONTROLn pin or OPERATION value. Unit always powers up with
sequencing. To turn unit on without sequencing, set TON_DELAY = ±.
1: Unit does not power up unless commanded by the CONTROLn pin and/or the OPERATION command
on the serial bus. If On_off_config[3:2] = ±±, the unit never powers up.
b[3]
b[2]
On_off_config_use_pmbus
On_off_config_use_control
Reserved
Controls how the unit responds to commands received via the serial bus.
±: Unit ignores the Operation_control[1:±] bits.
1: Unit responds to Operation_control[1:±]. Depending on On_off_config_use_control, the unit may also
require the CONTROLn pin to be asserted for the unit to start.
Controls how unit responds to the CONTROLn pin.
±: Unit ignores the CONTROLn pin.
1: Unit requires the CONTROLn pin to be asserted to start the unit. Depending on On_off_config_use_
pmbus the OPERATION command may also be required to instruct the device to start.
b[1]
b[±]
Not supported. Always returns 1.
On_off_config_control_fast_off CONTROLn pin turn off action when commanding the unit to turn off
±: Use the programmed TOFF_DELAY.
1: Turn off the output and stop transferring energy as quickly as possible, i.e. pull V
low
OUTENn
immediately.
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear any status faults that have been set. This command clears all bits in all
unpaged status registers, and the paged status registers selected by the current PAGE setting. At the same time, the
device negates (clears, releases) its contribution to ALERTB.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. See Clearing
Latched Faults for more information.
If the fault condition is present after the fault status is cleared, the fault status bit shall be set again and the host noti-
fied by the usual means.
Note: this command register does not respond to the global page command (PAGE=±xFF).
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LTC2978
PMBus COMMAND DESCRIPTION
WRITE_PROTECT
The WRITE_PROTECT command provides protection against accidental programming of the LTC2978 command reg-
isters. All supported commands may have their parameters read, regardless of the WRITE_PROTECT setting.
There are two levels of write protection:
•ꢀ Levelꢀ1:ꢀNothingꢀcanꢀbeꢀchangedꢀexceptꢀtheꢀlevelꢀofꢀwriteꢀprotectionꢀitself.ꢀValuesꢀcanꢀbeꢀreadꢀfromꢀallꢀpages.ꢀThisꢀ
setting can be stored to EEPROM.
•ꢀ Levelꢀ2:ꢀNothingꢀcanꢀbeꢀchangedꢀexceptꢀforꢀtheꢀlevelꢀofꢀprotection,ꢀchannelꢀon/offꢀstateꢀandꢀclearingꢀofꢀfaults.ꢀValuesꢀ
can be read from all pages. This setting can be stored to EEPROM.
WRITE_PROTECT Data Contents
BITS(S) SYMBOL
OPERATION
b[7:±] Write_protect[7:±] Level 1: 1±±±_±±±±b: Disable all writes except to the WRITE_PROTECT, PAGE, and STORE_USER_ALL commands.
Level 2: ±1±±_±±±±b: Disable all writes except to the WRITE_PROTECT, PAGE, STORE_USER_ALL, OPERATION, MFR_
PAGE_FF_MASK, and CLEAR_FAULTS.
±±±±_±±±±b: Enable writes to all commands.
xxxx_xxxxb: All other values reserved.
STORE_USER_ALL and RESTORE_USER_ALL
STORE_USER_ALL, RESTORE_USER_ALL commands provide access to User EEPROM space. Once a command is
stored in User EEPROM, it will be restored with an explicit restore command or when the part emerges from power-
2
on reset after power is applied. While either of these commands is being processed, the device will NACK I C writes.
STORE_USER_ALL.IssuingthiscommandwillstorealloperatingmemorycommandswithacorrespondingEEPROM
memory location. It is recommended that this command not be executed while a unit is enabled since all monitoring
is suspended while the operating memory is transferred to EEPROM.
RESTORE_USER_ALL. Issuing this command will restore all commands from EEPROM Memory. It is recommended
that this command not be executed while a unit is enabled since all monitoring is suspended while the EEPROM is
transferred to operating memory, and intermediate values from EEPROM may not be compatible with the values initially
stored in operating memory.
CAPABILITY
The CAPABILITY command provides a way for a host system to determine some key capabilities of the LTC2978. This
one byte command is read only.
CAPABILITY Data Contents
BITS(S) SYMBOL
OPERATION
b[7]
Capability_pec
Hard coded to 1 indicating Packet Error Checking is supported. Reading the Mfr_config_all_pec_en bit will indicate
whether PEC is currently required.
b[6]
b[ꢀ]
Capability_scl_max
Hard coded to 1 indicating the maximum supported bus speed is 4±±kHz.
Capability_smb_alert Hard coded to 1 indicating this device does have an ALERTB pin and does support the SMBus Alert Response
Protocol.
b[4:±] Reserved
Always returns ±.
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LTC2978
PMBus COMMAND DESCRIPTION
VOUT_MODE
This command is read only and specifies the mode and exponent for all commands with a L16 data format. See Data
Formats table on page 28.
VOUT_MODE Data Contents
BIT(S) SYMBOL
OPERATION
b[7:ꢀ] Vout_mode_type
Reports linear mode. Hard wired to ±±±b.
b[4:±] Vout_mode_parameter Linear mode exponent. ꢀ-bit two’s complement integer. Hardwired to ±x13 (–13 decimal).
OUTPUT VOLTAGE RELATED COMMANDS
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT, VOUT_OV_
WARN_LIMIT, VOUT_UV_WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and POWER_GOOD_OFF
These commands all use the same format and provide various servo, margining, and supervising limits for a chan-
nel’s output voltage. When odd channels are configured to measure current, the OV_WARN_LIMIT, UV_WARN_LIMIT,
OV_FAULT_LIMIT and UV_FAULT_LIMIT commands are not supported.
Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Vout_command[1ꢀ:±],
Vout_max[1ꢀ:±],
These commands relate to output voltage. The data uses the L16 format.
Units: V
Vout_margin_high[1ꢀ:±],
Vout_margin_low[1ꢀ:±],
Vout_ov_fault_limit[1ꢀ:±],
Vout_ov_warn_limit[1ꢀ:±],
Vout_uv_warn_limit[1ꢀ:±],
Vout_uv_fault_limit[1ꢀ:±],
Power_good_on[1ꢀ:±],
Power_good_off[1ꢀ:±]
INPUT VOLTAGE RELATED COMMANDS
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and VIN_UV_FAULT_
LIMIT
These commands use the same format and provide voltage supervising limits for V .
IN
Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Vin_on[1ꢀ:±],
Vin_off[1ꢀ:±],
These commands relate to input voltage. The data uses the L11 format.
Units: V.
Vin_ov_fault_limit[1ꢀ:±],
Vin_ov_warn_limit[1ꢀ:±],
Vin_uv_warn_limit[1ꢀ:±],
Vin_uv_fault_limit[1ꢀ:±]
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LTC2978
PMBus COMMAND DESCRIPTION
TEMPERATURE RELATED COMMANDS
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_LIMIT and UT_FAULT_LIMIT
These commands provide supervising limits for temperature.
Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Ot_fault_limit[1ꢀ:±], The data uses the L11 format.
Ot_warn_limit[1ꢀ:±], Units: °C.
Ut_warn_limit[1ꢀ:±],
Ut_fault_limit[1ꢀ:±]
TIMER LIMITS
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT and TOFF_DELAY
These commands share the same format and provide sequencing and timer fault and warning delays in ms.
TON_DELAY is the amount time in ms that elapses after the channel has been allowed on (usually due to CONTROLn
pin or OPERATION command) until the channel enables the power supply. This delay is counted using SHARE_CLK
only.
TON_RISE is the amount of time in ms that elapses after the power supply has been enabled until the LTC2978’s DAC
soft connects and servos the output voltage to the desired level if Mfr_dac_mode = ±±b. This delay is counted using
SHARE_CLK only.
TON_MAX_FAULT_LIMIT is the maximum amount of time that the power supply being controlled by the LTC2978 can
attempt to power up the output without reaching the VOUT_UV_FAULT_LIMIT. If the output reaches VOUT_UV_FAULT_
LIMIT prior to TON_MAX_FAULT_LIMIT, the LTC2978 unmasks the VOUT_UV_FAULT_LIMIT threshold. If it does not,
then a TON_MAX_FAULT is declared. (Note that a value of zero means there is no limit to how long the power supply
can attempt to bring up its output voltage.) This delay is counted using SHARE_CLK only.
TOFF_DELAY is the amount of time that elapses after the CONTROLn pin and/or OPERATION command is deasserted
until the channel is disabled (soft-off). This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used.
Data Contents
BIT(S) SYMBOL
b[1ꢀ:±] Ton_delay[1ꢀ:±],
Ton_rise[1ꢀ:±],
OPERATION
The data uses the L11 format.
The internal timers operate on a 1±µs internal clock. The SHARE_CLK pin may be used to synchronize the
1±µs timer.
Ton_max_fault_limit[1ꢀ:±],
Toff_delay[1ꢀ:±],
Delays are rounded to the nearest 1±µs
Units: ms. Max value: 6ꢀꢀms
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LTC2978
PMBus COMMAND DESCRIPTION
FAULT RESPONSE FOR VOLTAGES MEASURED BY THE HIGH SPEED SUPERVISOR
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE
The fault response documented here is for voltages that are measured by the high speed supervisor. These voltages
are measured over a short period of time and may require a deglitch period. Note that in addition to the response
described by these commands, the LTC2978 will also:
•ꢀ Setꢀtheꢀappropriateꢀbit(s)ꢀinꢀtheꢀSTATUS_BYTE
•ꢀ Setꢀtheꢀappropriateꢀbit(s)ꢀinꢀtheꢀSTATUS_WORD
•ꢀ Set the appropriate bit in the corresponding STATUS_VOUT register, and
•ꢀ NotifyꢀtheꢀhostꢀbyꢀpullingꢀtheꢀALERTBꢀpinꢀlow.ꢀ
Note: Odd numbered channels configured for high resolution ADC measurements (for current measurement) will not
respond to OV/UV faults or warnings.
Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Vout_ov_fault_response_action, Response action:
Vout_uv_fault_response_action ±±b: The unit continues operation without interruption.
±1b: The unit continues operating for the delay time specified by bits[2:±] in increments of ts_vs. (See
Electrical Characteristics Table, Voltage Supervisor Characteristics section).
If the fault is still present at the end of the delay time, the unit shuts down and responds as programmed in
the retry setting (bits [ꢀ:3]).
1Xb: The device shuts down and responds according to the retry setting in bits [ꢀ:3].
Response retry behavior:
b[ꢀ:3] Vout_ov_fault_response_retry,
Vout_uv_fault_response_retry
±±±b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
±±1b-111b: The PMBus device attempts to restart continuously, without limitation, at intervals of Mfr_retry_
delay, until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
b[2:±] Vout_ov_fault_response_delay, This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
delay to deglitch fast faults.
Vout_uv_fault_response_delay
±±±b: The unit turns off immediately.
±±1b-111b: The unit turns off after b[2:±] samples at the sampling period of ts_vs (12.2µs typical).
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LTC2978
PMBus COMMAND DESCRIPTION
FAULT RESPONSE FOR VALUES MEASURED BY THE ADC
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_RESPONSE
The fault response documented here is for values that are measured by the ADC. These values are measured over a
longer period of time and are not deglitched. Note that in addition to the response described by these commands, the
LTC2978 will also:
•ꢀ Setꢀtheꢀappropriateꢀbit(s)ꢀinꢀtheꢀSTATUS_BYTE
•ꢀ Setꢀtheꢀappropriateꢀbit(s)ꢀinꢀtheꢀSTATUS_WORD
•ꢀ SetꢀtheꢀappropriateꢀbitꢀinꢀtheꢀcorrespondingꢀSTATUS_VINꢀorꢀSTATUS_TEMPERATUREꢀregister,ꢀand
•ꢀ NotifyꢀtheꢀhostꢀbyꢀpullingꢀtheꢀALERTBꢀpinꢀlow.
Data Contents
BIT(S) SYMBOL
OPERATION
b[7:6] Ot_fault_response_action,
Ut_fault_response_action,
Response action:
±±b: The unit continues operation without interruption.
Vin_ov_fault_response_action, ±1b to 11b: The device shuts down and responds according to the retry setting in bits [ꢀ:3].
Vin_uv_fault_response_action
b[ꢀ:3] Ot_fault_response_retry,
Response retry behavior:
Ut_fault_response_retry,
±±±b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
Vin_ov_fault_response_retry,
Vin_uv_fault_response_retry
±±1b-111b: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay,
until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed,
or another fault condition causes the unit to shut down.
b[2:±] Ot_fault_response_delay,
Ut_fault_response_delay,
Hard coded to ±±±b. The unit turns off immediately.
Vin_ov_fault_response_delay,
Vin_uv_fault_response_delay
TIMED FAULT RESPONSE
TON_MAX_FAULT_RESPONSE
This command defines the LTC2978 response to a TON_MAX_FAULT. It may be used to protect against a short-circuited
output at start-up. After start-up use VOUT_UV_FAULT_RESPONSE to protect against a short-circuited output.
The device also:
•ꢀ SetsꢀtheꢀHIGH_BYTEꢀbitꢀinꢀtheꢀSTATUS_BYTE,
•ꢀ SetsꢀtheꢀVOUTꢀbitꢀinꢀtheꢀSTATUS_WORD,
•ꢀ SetsꢀtheꢀTON_MAX_FAULTꢀbitꢀinꢀtheꢀSTATUS_VOUTꢀregister,ꢀand
•ꢀ NotifiesꢀtheꢀhostꢀbyꢀassertingꢀALERTB.
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LTC2978
PMBus COMMAND DESCRIPTION
TON_MAX_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
b[7:6] Ton_max_fault_response_action Response action:
±±b: The unit continues operation without interruption.
OPERATION
±1b: The unit continues operating for the delay time specified which for this type of fault corresponds to an
immediate shutdown. After shutting off, the device responds according to the retry settings in bits [ꢀ:3].
1Xb: The device shuts down and responds according to the retry setting in bits [ꢀ:3].
Response retry behavior:
b[ꢀ:3] Ton_max_fault_response_retry
±±±b: A zero value for the Retry Setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
±±1b-111b: The PMBus device attempts to restart continuously, without limitation, using Mfr_retry_delay,
until it is commanded OFF (by the CONTROLn pin or OPERATION command or both), bias power is removed,
or another fault condition causes the unit to shut down.
b[2:±] Ton_max_fault_response_delay Hard coded to ±±±b. The unit turns off immediately.
Clearing Latched Faults
Latched faults are reset by toggling the CONTROL pin, using the OPERATION command, or removing and reapplying
the bias voltage to the V
pin. All fault and warning conditions result in the ALERTB pin being asserted low and
IN_SNS
the corresponding bits being set in the status registers. The CLEAR_FAULTS command resets the contents of the status
registers and de-asserts the ALERTB output, but it does not clear a faulted off state nor allow a channel to turn back on.
STATUS COMMANDS
STATUS_BYTE:
The STATUS_BYTE command returns the summary of the most critical faults or warnings which have occurred, as
shown in the following table. STATUS_BYTE is a subset of STATUS_WORD and duplicates the same information.
STATUS_BYTE Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
b[6]
b[ꢀ]
b[4]
b[3]
b[2]
b[1]
b[±]
Status_byte_busy
Same as Status_word_busy
Same as Status_word_off
Same as Status_word_vout_ov
Same as Status_word_iout_oc
Same as Status_word_vin_uv
Same as Status_word_temp
Same as Status_word_cml
Same as Status_word_high_byte
Status_byte_off
Status_byte_vout_ov
Status_byte_iout_oc
Status_byte_vin_uv
Status_byte_temp
Status_byte_cml
Status_byte_high_byte
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LTC2978
PMBus COMMAND DESCRIPTION
STATUS_WORD:
The STATUS_WORD command returns two bytes of information with a summary of the unit’s fault condition. Based
on the information in these bytes, the host can get more information by reading detailed status register.
The low byte of the STATUS_WORD is the same register as the STATUS_BYTE command.
STATUS_WORD Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ] Status_word_vout
b[14] Status_word_iout
b[13] Status_word_input
b[12] Status_word_mfr
An output voltage fault or warning has occurred. See STATUS_VOUT.
Notsupported.Alwaysreturns±.
An input voltage fault or warning has occurred. See STATUS_INPUT.
A manufacturer specific fault has occurred. See STATUS_MFR_SPECIFIC.
b[11] Status_word_power_not_good The POWER_GOOD signal, if present is negated. Power is not good.
b[1±] Status_word_fans
Notsupported.Alwaysreturns±.
b[9]
b[8]
b[7]
b[6]
Status_word_other
Status_word_unknown
Status_word_busy
Status_word_off
Notsupported.Alwaysreturns±.
Notsupported.Alwaysreturns±.
Device busy when PMBus command received. See OPERATION: Processing Commands.
This bit is asserted if the unit is not providing power to the output, regardless of the reason, including
simply not being enabled. The off bit is clear if unit is allowed to provide power to the output.
b[ꢀ]
b[4]
b[3]
b[2]
b[1]
b[±]
Status_word_vout_ov
Status_word_iout_oc
Status_word_vin_uv
Status_word_temp
Status_word_cml
An output overvoltage fault has occured.
Notsupported.Alwaysreturns±.
A V undervoltage fault has occurred.
IN
A temperature fault or warning has occurred. See STATUS_TEMPERATURE.
A communication, memory or logic fault has occurred. See STATUS_CML.
A fault/warning not listed in b[7:1] has occurred.
Status_word_high_byte
STATUS_VOUT
The STATUS_VOUT command returns the summary of the output voltage faults or warnings which have occurred, as
shown in the following table:
STATUS_VOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_vout_ov_fault
b[6] Status_vout_ov_warn
b[ꢀ] Status_vout_uv_warn
b[4] Status_vout_uv_fault
b[3] Status_vout_max_fault
Overvoltage fault.
Overvoltage warning.
Undervoltage warning
Undervoltage fault.
VOUT_MAX fault. An attempt has been made to set the output voltage to a value higher than allowed by the
VOUT_MAX command.
b[2] Status_vout_ton_max_fault
b[1] Status_vout_toff_max_warn
b[±] Status_vout_tracking_error
TON_MAX_FAULT sequencing fault.
Not supported. Always returns ±.
Not supported. Always returns ±.
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LTC2978
PMBus COMMAND DESCRIPTION
STATUS_INPUT
The STATUS_INPUT command returns the summary of the V faults or warnings which have occurred, as shown in
IN
the following table:
STATUS_INPUT Data Contents
BIT(S) SYMBOL
OPERATION
b[7]
b[6]
b[ꢀ]
b[4]
b[3]
b[2]
b[1]
b[±]
Status_input_ov_fault
V
V
V
V
Overvoltage fault
IN
IN
IN
IN
Status_input_ov_warn
Status_input_uv_warn
Status_input_uv_fault
Status_input_off
Overvoltage warning
Undervoltage warning
Undervoltage fault
Unit is off for insufficient input voltage.
Not supported. Always returns ±.
Not supported. Always returns ±.
Not supported. Always returns ±.
I
IN
I
IN
overcurrent fault
overcurrent warn
PIN overpower warn
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns the summary of the temperature faults or warnings which have oc-
curred, as shown in the following table:
STATUS_TEMPERATURE Data Contents
Bit(s) Symbol
Operation
b[7] Status_temperature_ot_fault
Overtemperature fault.
b[6] Status_temperature_ot_warn Overtemperature warning.
b[ꢀ] Status_temperature_ut_warn Undertemperature warning.
b[4] Status_temperature_ut_fault
b[3] Reserved
Undertemperature fault.
Reserved. Always returns ±.
Reserved. Always returns ±.
Reserved. Always returns ±.
Reserved. Always returns ±.
b[2] Reserved
b[1] Reserved
b[±] Reserved
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LTC2978
PMBus COMMAND DESCRIPTION
STATUS_CML
The STATUS_CML command returns the summary of the communication, memory and logic faults or warnings which
have occurred, as shown in the following table:
STATUS_CML Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Status_cml_cmd_fault
b[6] Status_cml_data_fault
b[ꢀ] Status_cml_pec_fault
Illegal or unsupported command fault has occurred.
Illegal or unsupported data received.
A PEC fault has occurred. Note: PEC checking is always active in the LTC2978. Any extra byte received before a
STOP will set Status_cml_pec_fault unless the extra byte is a matching PEC byte.
b[4] Status_cml_memory_fault
A fault has occurred in the NVM. (EEPROM).
b[3] Status_cml_processor_fault Not supported, always returns ±.
b[2] Reserved
Reserved, always returns ±.
b[1] Status_cml_pmbus_fault
A communication fault other than ones listed in this table has occurred. This is a catch all category for illegally
2
formed I C/SMBus commands (Example: An address byte with read =1 received immediately after a START).
b[±] Status_cml_unknown_fault Not supported, always returns ±.
STATUS_MFR_SPECIFIC
TheSTATUS_MFR_SPECIFICcommandreturnsmanufacturerspecificstatusflags. BitsmarkedFAULT=Noareintended
to support polled handshaking; these are not latched nor do they assert ALERTB. Bits marked FAULT = Yes assert
ALERTB low and are cleared by CLEAR_FAULTS. Bits marked Channel = All can be read from any page.
STATUS_MFR_SPECIFIC Data Contents
BIT(S) SYMBOL
OPERATION
A V discharge fault occurred while attempting to enter the ON state
CHANNEL
FAULT
Yes
b[7] Status_mfr_discharge
b[6] Status_mfr_fault1_in
Current Page
OUT
This channel attempted to turn on while the FAULTBz1 pin was asserted low, Current Page
or this channel has shut down at least once in response to a FAULTBz1 pin
asserting low since the last CONTROLn pin toggle, OPERATION command
ON/OFF cycle or CLEAR_FAULTS command.
Yes
b[ꢀ] Status_mfr_fault±_in
This channel attempted to turn on while the FAULTBz± pin was asserted low, Current Page
or this channel has shut down at least once in response to a FAULTBz± pin
asserting low since the last CONTROLn pin toggle, OPERATION command
ON/OFF cycle or CLEAR_FAULTS command.
Yes
b[4] Status_mfr_servo_target_reached Servo target has been reached.
Current Page
Current Page
Current Page
No
No
b[3] Status_mfr_dac_connected
b[2] Status_mfr_dac_saturated
DAC is connected and driving V
pin.
DACP
A previous servo operation terminated with maximum or minimum DAC
value.
Yes
b[1] Status_mfr_vinen_faulted_off
b[±] Status_mfr_watchdog_fault
V
has been deasserted due to a V
fault.
All
All
No
IN_EN
OUT
A watchdog fault has occurred.
Yes
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LTC2978
PMBus COMMAND DESCRIPTION
ADC MONITORING COMMANDS
READ_VIN
This command returns the most recent ADC measured value of the voltage measured at the V
pin.
IN_SNS
READ_VIN Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Read_vin[1ꢀ:±] The data uses the L11 format.
Units: V
READ_VOUT
This command returns the most recent ADC measured value of the channel’s output voltage. When odd channels are
configured to measure current, the data contents use the L11 format with units in mV.
READ_VOUT Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Read_vout[1ꢀ:±] The data uses the L16 format.
Units: V
READ_VOUT Data Contents—for Odd Channels Configured to Measure Current
Bit(s) Symbol
Operation
The data uses the L11 format.
Units: mV
b[1ꢀ:±] Read_vout[1ꢀ:±]
READ_TEMPERATURE_1
This command returns the most recent ADC measured value of junction temperature in °C as determined by the
LTC2978’s internal temperature sensor.
READ_TEMPERATURE_1 Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Read_temperature_1 [1ꢀ:±] The data uses the L11 format.
Units: °C.
PMBUS_REVISION
The PMBUS_REVISION command register is read only and reports the LTC2978 compliance to the PMBus standard
revision 1.1.
PMBUS_REVISION Data Contents
BIT(S) SYMBOL
OPERATION
b[7:±] PMBus_rev Reports the PMBus standard revision compliance. This is hard-coded to ±x11 for revision 1.1.
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LTC2978
PMBus COMMAND DESCRIPTION
MANUFACTURER SPECIFIC COMMANDS
MFR_CONFIG_LTC2978
This command is used to configure various manufacturer specific operating parameters for each channel.
MFR_CONFIG_LTC2978 Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:12] Reserved
Don’t care. Always returns ±.
b[11] Mfr_config_fast_servo_off
Disables fast servo when margining or trimming output voltages:
±: fast-servo enabled.
1: fast-servo disabled.
b[1±] Mfr_config_supervisor_resolution Selects supervisor resolution:
±: high resolution – 4mV/LSB, range for V
– V
is ±V to 3.8V.
is ±V to 6.±V.
VSENSEPn
VSENSEMn
1: low resolution – 8mV/LSB, range for V
– V
VSENSEPn
VSENSEMn
b[9] Mfr_config_adc_hires
Selects ADC resolution for odd channels. This is typically used to measure current. Ignored for even
channels (they always use low resolution).
±: low resolution – 122µV/LSB.
1: high resolution – 1ꢀ.6µV/LSB.
b[8] Mfr_config_controln_sel
Selects the active control pin input (CONTROL± or CONTROL1) for this channel.
±: Select CONTROL± pin.
1: Select CONTROL1 pin.
b[7] Mfr_config_servo_continuous
Select whether the UNIT should continuously servo V
after it has reached a new margin or nominal
OUT
target. Only applies when Mfr_config_dac_mode = ±±b.
±: Do not continuously servo V after reaching initial target.
OUT
1: Continuously servo V
to target.
OUT
b[6] Mfr_config_servo_on_warn
b[ꢀ:4] Mfr_config_dac_mode
Control re-servo on warning feature. Only applies when Mfr_config_dac_mode = ±±b and
Mfr_config_servo_continuous = ±.
±: Do not allow the unit to re-servo when a V
warning threshold is met or exceeded.
OUT
1: Allow the unit to re-servo V
to nominal target if
OUT
V
V
≥ V(Vout_ov_warn_limit) or
≤ V(Vout_uv_warn_limit).
OUT
OUT
Determines how DAC is used when channel enters ON state or is already in ON state.
±±: Soft connect (if needed) and servo to target. Wait for TON_RISE if just entering ON state.
±1: DAC not connected.
1±: DAC connected using value from MFR_DAC command.
11: DAC is soft connected. After soft connect is complete MFR_DAC may be written.
b[3] Mfr_config_vo_en_wpu_en
b[2] Mfr_config_vo_en_wpd_en
V
pin charge pumped, current-limited pull-up enable.
OUT_EN
±: Disable weak pull-up. V
1: Use weak current-limited pull-up on V
For channels 4-7 this bit is treated as a ± regardless of its value.
pin driver is three-stated when channel is on.
OUT_EN
pin when the channel is on.
OUT_EN
V
pin current-limited pull-down enable.
OUT_EN
±: Use a fast N-channel device to pull down V
pin when the channel is off for any reason.
OUT_EN
1: Use weak current-limited pull-down to discharge V
pin when channel is off due to soft stop by the
OUT_EN
CONTROLn pin and/or OPERATION command. If the channel is off due to a fault, use the fast pull-down on
V
pin.
OUT_EN
For channels 4-7 this bit is treated as a ± regardless of its value.
b[1] Mfr_config_dac_gain
b[±] Mfr_config_dac_pol
DAC buffer gain.
±: Select DAC buffer gain dac_gain_± (1.38V full-scale)
1: Select DAC buffer gain dac_gain_1 (2.6ꢀV full-scale)
DAC output polarity.
±: Encodes negative (inverting) DC/DC converter trim input.
1: Encodes positive (noninverting) DC/DC converter trim input.
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_CONFIG_ALL_LTC2978
This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed
from any PAGE setting.
MFR_CONFIG_ALL_LTC2978 Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Mfr_config_fault_log_enable
Enable fault logging to NVM in response to Fault.
±: Fault logging to NVM is disabled
1: Fault logging to NVM is enabled
VIN_ON rising edge to clear all latched faults
±: VIN_ON clear faults feature is disabled
1: VIN_ON clear faults feature is enabled
Selects active polarity of control1 pin.
±: Active low (pull pin low to start unit)
1: Active high (pull pin high to start unit)
Selects active polarity of control± pin.
±: Active low (pull pin low to start unit)
1: Active high (pull pin high to start unit)
b[6] Mfr_vin_on_clr_faults_en
b[ꢀ] Mfr_config_control1_pol
b[4] Mfr_config_control±_pol
b[3] Mfr_config_vin_share_enable
Allow this unit to hold share-clock pin low when VIN_ON has fallen below VIN_OFF. When enabled, this unit
will also turn all channels off in response to share-clock being held low.
±: Share-clock inhibit is disabled
1: Share-clock inhibit is enabled
PMBus packet error checking enable.
±: PEC is accepted but not required
1: PEC is required
b[2] Mfr_config_all_pec_en
b[1] Mfr_config_all_longer_pmbus_ Increase PMBus timeout internal by a factor of 8. Recommended for fault logging.
timeout
±: PMBus timeout is not multiplied by a factor of 8
1: PMBus timeout is multiplied by a factor of 8
b[±] Mfr_config_all_vinen_wpu_dis
V
IN_EN
charge pumped, current-limited pull-up disable.
±: Use weak current-limited pull-up on V
after power-up, as long as no faults have forced V
off.
IN_EN
IN_EN
1: Disable weak pull-up. V
off.
driver is three-stated after power-up as long as no faults have forced V
IN_EN
IN_EN
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_FAULTz0_PROPAGATE, MFR_FAULTz1_PROPAGATE
These manufacturer specific commands enable channels that have faulted off to propagate that state to the appropri-
ate fault pin. Faulted off states for pages ± through 3 can only be propagated to pins FAULTB±± and FAULTB±1; this is
referred to as zone ±. Faulted off states for pages 4 through 7 can only be propagated to pins FAULTB1± and FAULTB11;
this is referred to as zone 1. The z designator in the command name is used to indicate that this command affects
different zones depending on the page. See Figure 19.
Note that pulling a fault pin low will have no affect for channels that have MRF_FAULTBzn_RESPONSE set to ±. The
channel continues operation without interruption. This fault response is called no action in LTpowerPlay™.
MFR_FAULTz0_PROPAGATE Data Content
BIT(S) SYMBOL
OPERATION
b[7:1]
b[±]
Reserved
Don’t care. Always returns ±.
Enable fault propagation.
Mfr_faultbz±_propagate
For pages ± through 3, zone ±
±: Channel’s faulted off state does not assert FAULTB±± low.
1: Channel’s faulted off state asserts FAULTB±± low.
For pages 4 through 7, zone 1
±: Channel’s faulted off state does not assert FAULTB1± low.
1: Channel’s faulted off state asserts FAULTB1± low.
MFR_FAULTz1_PROPAGATE Data Content
BIT(S) SYMBOL
OPERATION
b[7:1]
b[±]
Reserved
Don’t care. Always returns ±.
Mfr_faultbz1_propagate
Enable fault propagation.
For pages ± through 3, zone ±
±: Channel’s faulted off state does not assert FAULTB±1 low.
1: Channel’s faulted off state asserts FAULTB±1 low.
For pages 4 through 7, zone 1
±: Channel’s faulted off state does not assert FAULTB11 low.
1: Channel’s faulted off state asserts FAULTB11 low.
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_PWRGD_EN
This command register controls the mapping of the watchdog and channel power good status to the PWRGD pin. Note
that odd numbered channels whose ADC is in high res mode do not contribute to power good.
MFR_PWRGD_EN Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:9] Reserved
Read only, always returns ±s.
Watchdog
b[8] Mfr_pwrgd_en_wdog
1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to
determine when the PWRGD pin gets asserted.
± = Watchdog timer does not affect the PWRGD pin.
Channel 7
b[7] Mfr_pwrgd_en_chan7
b[6] Mfr_pwrgd_en_chan6
b[ꢀ] Mfr_pwrgd_en_chanꢀ
b[4] Mfr_pwrgd_en_chan4
b[3] Mfr_pwrgd_en_chan3
b[2] Mfr_pwrgd_en_chan2
b[1] Mfr_pwrgd_en_chan1
b[±] Mfr_pwrgd_en_chan±
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
± = PRWGD status for this channel does not affect the PWRGD pin.
Channel 6
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
± = PRWGD status for this channel does not affect the PWRGD pin.
Channel ꢀ
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
± = PRWGD status for this channel does not affect the PWRGD pin.
Channel 4
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
± = PRWGD status for this channel does not affect the PWRGD pin.
Channel 3
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
± = PRWGD status for this channel does not affect the PWRGD pin.
Channel 2
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
± = PRWGD status for this channel does not affect the PWRGD pin.
Channel 1
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
± = PRWGD status for this channel does not affect the PWRGD pin.
Channel ±
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
± = PRWGD status for this channel does not affect the PWRGD pin.
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_FAULTB00_RESPONSE, MFR_FAULTB01_RESPONSE, MFR_FAULTB10_RESPONSE and MFR_
FAULTB11_RESPONSE
These manufacturer specific commands share the same format and specify the response to assertions of the FAULTB
pins. For fault zone ±, MFR_FAULTB±±_RESPONSE determines whether channels ± to 3 shut off when the FAULTB±±
pin is asserted, and MFR_FAULTB±1_RESPONSE determines whether channels ± to 3 shut off when the FAULTB±1
pin is asserted. For fault zone 1, MFR_FAULTB1±_RESPONSE determines whether channels 4 to 7 shut off when the
FAULTB1± pin is asserted, and MFR_FAULTB11_RESPONSE determines whether channels 4 to 7 shut off when the
FAULTB11 pin is asserted. When a channel shuts off in response to a FAULTB pin, the ALERTB pin is asserted low and
the appropriate bit is set in the STATUS_MFR_SPECIFIC register. For a graphical explanation, see the switches on the
left hand side of Figure 19, Channel Fault Management Block Diagram.
Data Contents—Fault Zone 0 Response Commands
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Read only, always returns ±s.
b[3] Mfr_faultb±±_response_chan3, Channel 3 response.
Mfr_faultb±1_response_chan3 ±: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 1±µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[2] Mfr_faultb±±_response_chan2, Channel 2 response.
Mfr_faultb±1_response_chan2 ±: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 1±µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[1] Mfr_faultb±±_response_chan1, Channel 1 response.
Mfr_faultb±1_response_chan1 ±: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 1±µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[±] Mfr_faultb±±_response_chan±, Channel ± response.
Mfr_faultb±1_response_chan± ±: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 1±µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
Data Contents—Fault Zone 1 Response Commands
BIT(S) SYMBOL
OPERATION
b[7:4] Reserved
Read only, always returns ±s.
b[3] Mfr_faultb1±_response_chan7, Channel 7 response.
Mfr_faultb11_response_chan7 ±: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 1±µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[2] Mfr_faultb1±_response_chan6, Channel 6 response.
Mfr_faultb11_response_chan6 ±: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 1±µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[1] Mfr_faultb1±_response_chanꢀ, Channel ꢀ response.
Mfr_faultb11_response_chanꢀ ±: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 1±µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
b[±] Mfr_faultb1±_response_chan4, Channel 4 response.
Mfr_faultb11_response_chan4 ±: The channel continues operation without interruption.
1: The channel shuts down if the corresponding FAULTBzn pin is still asserted after 1±µs. When the FAULTBzn
pin subsequently deasserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_VINEN_OV_FAULT_RESPONSE
This command register determines whether V
forced off.
over voltage faults from a given channel cause the V
pin to be
IN_EN
OUT
MFR_VINEN_OV_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
Response to channel 7 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
b[7] Mfr_vinen_ov_fault_response_chan7
IN_EN
± = Leave V
as-is.
IN_EN
b[6] Mfr_vinen_ov_fault_response_chan6
b[ꢀ] Mfr_vinen_ov_fault_response_chanꢀ
b[4] Mfr_vinen_ov_fault_response_chan4
b[3] Mfr_vinen_ov_fault_response_chan3
b[2] Mfr_vinen_ov_fault_response_chan2
b[1] Mfr_vinen_ov_fault_response_chan1
b[±] Mfr_vinen_ov_fault_response_chan±
Response to channel 6 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel ꢀ VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel 4 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel 3 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel 2 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel 1 VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel ± VOUT_OV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_VINEN_UV_FAULT_RESPONSE
This command register determines whether V
be forced off.
undervoltage faults from a given channel cause the V
pin to
OUT
IN_EN
MFR_VINEN_UV_FAULT_RESPONSE Data Contents
BIT(S) SYMBOL
OPERATION
Response to channel 7 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
b[7] Mfr_vinen_uv_fault_response_chan7
IN_EN
± = Leave V
as-is.
IN_EN
b[6] Mfr_vinen_uv_fault_response_chan6
b[ꢀ] Mfr_vinen_uv_fault_response_chanꢀ
b[4] Mfr_vinen_uv_fault_response_chan4
b[3] Mfr_vinen_uv_fault_response_chan3
b[2] Mfr_vinen_uv_fault_response_chan2
b[1] Mfr_vinen_uv_fault_response_chan1
b[±] Mfr_vinen_uv_fault_response_chan±
Response to channel 6 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel ꢀ VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel 4 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel 3 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel 2 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel 1 VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
Response to channel ± VOUT_UV_FAULT.
1 = Disable V via fast pull-down.
IN_EN
± = Leave V
as-is.
IN_EN
MFR_RETRY_DELAY
ThiscommanddeterminestheretryintervalwhentheLTC2978isinretrymodeinresponsetoafaultcondition.
MFR_RETRY_DELAY Data Contents
BIT(S) SYMBOL
b[1ꢀ:±] Mfr_retry_delay The data uses the L11 format.
This delay is counted using SHARE_CLK only.
OPERATION
Delays are rounded to the nearest 2±±µs.
Units: ms. Max delay is 13.1 sec.
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_RESTART_DELAY
ThiscommandsetstheminimumofftimeofaCONTROLinitiatedrestart.IftheCONTROLpinistoggledoffforatleast1±µs
thenon,alldependentchannelsaredisabled,heldoffforatime=Mfr_restart_delay,thensequencedbackon.CONTROLn
pin transitions whose OFF time exceeds Mfr_restart_delay are not affected by this command. A value of all zeros disables
thisfeature.
MFR_RESTART_DELAY Data Contents
BIT(S) SYMBOL
b[1ꢀ:±] Mfr_restart_delay The data uses the L11 format.
This delay is counted using SHARE_CLK only.
OPERATION
Delays are rounded to the nearest 2±±µs.
Units: ms. Max delay is 13.1 sec.
MFR_VOUT_PEAK
This command returns the maximum ADC measured value of the channel’s output voltage. This command is not sup-
ported for odd channels that are configured to measure current. This register is reset to ±xF8±± (±.±) when the LTC2978
emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VOUT_PEAK Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Mfr_vout_peak[1ꢀ:±] The data uses the L16 format.
Units: V.
MFR_VIN_PEAK
2ꢀ
This command returns the maximum ADC measured value of the input voltage. This register is reset to ±x7C±± (–2 )
when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VIN_PEAK Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Mfr_vin_peak[1ꢀ:±] The data uses the L11 format.
Units: V
MFR_TEMPERATURE_PEAK
This command returns the maximum ADC measured value of junction temperature in °C as determined by the LTC2978’s
2ꢀ
internal temperature sensor. This register is reset to ±x7C±± (–2 ) when the LTC2978 emerges from power-on reset
or when a CLEAR_FAULTS command is executed.
MFR_TEMPERATURE_PEAK Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Mfr_temperature_peak[1ꢀ:±] The data uses the L11 format.
Units: °C.
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_DAC
This command register allows the user to directly program the 1±-bit DAC. Manual DAC writes require the channel to
be in the ON state,TON_RISE to have expired and MFR_CONFIG_LTC2978 b[ꢀ:4] = 1±b or 11b. Writing MFR_CONFIG_
LTC2978 b[ꢀ:4] = 1±b commands the DAC to hard connect with the value in Mfr_dac_direct_val. Writing b[ꢀ:4] = 11b
commands the DAC to soft connect. Once the DAC has soft connected, Mfr_dac_direct_val returns the value that al-
lowed the DAC to be connected without perturbing the power supply.
MFR_DAC Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:1±] Reserved
Read only, always returns ±.
b[9:±] Mfr_dac_direct_val DAC code value.
MFR_POWERGOOD_ASSERTION_DELAY
This command register allows the user to program the delay from when the internal power good signal becomes valid
until the power good output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 2±±µs. The read value
of this command always returns what was last written and does not reflect internal limiting.
MFR_POWERGOOD_ASSERTION_DELAY Data Contents
BIT(S) SYMBOL
b[1ꢀ:±] Mfr_powergood_assertion_delay The data uses the L11 format.
This delay is counted using SHARE_CLK if available, otherwise the internal oscillator is used.
OPERATION
Delays are rounded to the nearest 2±±µs.
Units: ms. Max delay is 13.1 sec.
WATCHDOG OPERATION
A non zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the WDI/
RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output is optionally
deassertedandthenreassertedafterMFR_PWRGD_ASSERTION_DELAYms.Writing±toeithertheMFR_WATCH_DOG_T
or MFR_WATCHDOG_T_FIRST registers will disable the timer.
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T
The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval
following assertion of the POWER GOOD signal, assuming the POWER GOOD signal reflects the status of the watchdog
timer. If assertion of POWER GOOD is not conditioned by the watchdog timer’s status, then MFR_WATCHDOG_T_FIRST
applies to the first timing interval after the timer is enabled. Writing a value of ±ms to the MFR_WATCHDOG_T_FIRST
register disables the watchdog timer.
The MFR_WATCHDOG_T register allows the user to program watchdog time intervals subsequent to the MFR_
WATCHDOG_T_FIRST timing interval. Writing a value of ±ms to the MFR_WATCHDOG_T register disables the
watchdog timer. A non-zero write to MFR_WATCHDOG_T will reset the watchdog timer.
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_WATCHDOG_T_POR and MFR_WATCHDOG_T Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Mfr_watchdog_t_first The data uses the L11 format.
Mfr_watchdog_t
These timers operate on an internal clock. The Mfr_watchdog_t timer will align to SHARE_CLK if it is running.
Delays are rounded to the nearest 1±µs for _t and 1ms for _t_first.
Writing a zero value for Y to the Mfr_watchdog_t or Mfr_watchdog_t_first registers will disable the watchdog timer.
Units: ms. Max timeout is ±.6 sec for _t and 6ꢀ sec for _t_first
MFR_PAGE_FF_MASK
The MFR_PAGE_FF_MASK command is used to select which channels respond when the global page command
(PAGE=±xFF) is in use.
MFR_PAGE_FF_MASK Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Mfr_page_ff_mask_chan7
Channel 7 masking of global page command (PAGE=±xFF) accesses
± = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 6 masking of global page command (PAGE=±xFF) accesses
± = ignore global page command accesses
b[6] Mfr_page_ff_mask_chan6
b[ꢀ] Mfr_page_ff_mask_chanꢀ
b[4] Mfr_page_ff_mask_chan4
b[3] Mfr_page_ff_mask_chan3
b[2] Mfr_page_ff_mask_chan2
b[1] Mfr_page_ff_mask_chan1
b[±] Mfr_page_ff_mask_chan±
1 = fully respond to global page command accesses
Channel ꢀ masking of global page command (PAGE=±xFF) accesses
± = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 4 masking of global page command (PAGE=±xFF) accesses
± = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 3 masking of global page command (PAGE=±xFF) accesses
± = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 2 masking of global page command (PAGE=±xFF) accesses
± = ignore global page command accesses
1 = fully respond to global page command accesses
Channel 1 masking of global page command (PAGE=±xFF) accesses
± = ignore global page command accesses
1 = fully respond to global page command accesses
Channel ± masking of global page command (PAGE=±xFF) accesses
± = ignore global page command accesses
1 = fully respond to global page command accesses
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LTC2978
PMBus COMMAND DESCRIPTION
MFR_PADS
The MFR_PADS command provides read only access to slow frequency digital pads. The input values presented in
bits[9:±] are before any deglitching logic.
MFR_PADS_PWRGD_DRIVE Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ] Mfr_pads_pwrgd_drive
± = PWRGD pad is being driven low by this chip
1 = PWRGD pad is not being driven low by this chip
± = ALERTB pad is being driven low by this chip
1 = ALERTB pad is not being driven low by this chip
b[14] Mfr_pads_alertb_drive
b[13:1±] Mfr_pads_faultb_drive[3.±] Bit[3] used for FAULTB±± pad, bit[2] used for FAULTB±1 pad, bit[1] used for FAULTB1± pad, bit[±] used for
FAULTB11 pad as follows:
± = FAULTBzn pad is being driven low by this chip
1 = FAULTBzn pad is not being driven low by this chip
b[9:8] Mfr_pads_asel1[1:±]
b[7:6] Mfr_pads_asel±[1:±]
11: Logic high detected on ASEL1 input pad
1±: ASEL1 input pad is floating
±1: Reserved
±±: Logic low detected on ASEL1 input pad
11: Logic high detected on ASEL± input pad
1±: ASEL± input pad is floating
±1: Reserved
±±: Logic low detected on ASEL± input pad
1: Logic high detected on CONTROL1 pad
±: Logic low detected on CONTROL1 pad
1: Logic high detected on CONTROL± pad
±: Logic low detected on CONTROL± pad
b[ꢀ] Mfr_pads_control1
b[4] Mfr_pads_control±
b[3:±] Mfr_pads_faultb[3:±]
Bit[3] used for FAULTB±± pad, bit[2] used for FAULTB±1 pad, bit[1] used for FAULTB1± pad, bit[±] used for
FAULTB11 pad as follows:
1: Logic high detected on FAULTBzn pad
±: Logic low detected on FAULTBzn pad
MFR_I2C_BASE_ADDRESS
2
The MFR_I2C_BASE_ADDRESS command determines the base value for the I C/SMBus address byte. Offsets of ±
2
to 9 are added to this base address to make the device I C/SMBus address. The part responds to the device address.
MFR_I2C_BASE_ADDRESS Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Reserved
Read only, always returns ±.
2
b[6:±] i2c_base_address This 7-bit value determines the base value of the 7-bit I C/SMBus address. See Operation Section: Device Address.
MFR_SPECIAL_ID
This register contains the manufacturer ID for the LTC2978.
MFR_SPECIAL_ID Data Contents
BIT(S)
SYMBOL
OPERATION
b[1ꢀ:±]
Mfr_special_id
Read only, always returns ±x±121
2978fc
52
LTC2978
PMBus COMMAND DESCRIPTION
MFR_SPECIAL_LOT
These paged registers contain information that identifies the user configuration that was programmed at the factory.
MFR_SPECIAL_LOT Data Contents
BIT(S)
SYMBOL
OPERATION
b[7:±]
Mfr_special_lot
Contains the LTC default special lot number. Contact the factory to request a custom factory programmed user configura-
tion and special lot number.
MFR_VOUT_DISCHARGE_THRESHOLD
This register contains the coefficient that multiplies VOUT_COMMAND in order to determine the OFF thresh-
old voltage for the associated output. If the output voltage has not decayed below MFR_VOUT_DISCHARGE_
THRESHOLDꢀ•ꢀVOUT_COMMANDꢀpriorꢀtoꢀtheꢀchannelꢀbeingꢀcommandedꢀtoꢀenter/re-enterꢀtheꢀONꢀstate,ꢀbitꢀ[7]ꢀinꢀtheꢀ
STATUS_MFR_SPECIFIC register will be set and the ALERTB pin will be asserted low. In addition, the channel will not
enter the ON state until the output has decayed below its OFF threshold voltage.
Other channels can be held off if a particular output has failed to discharge by using the bidirectional FAULTBzn pins
(refer to the MFR_FAULTBzn_RESPONSE and MFR_FAULTBzn_PROPAGATE registers).
MFR_VOUT_DISCHARGE_THRESHOLD Data Contents
BIT(S)
SYMBOL
OPERATION
b[1ꢀ:±]
Mfr_vout_discharge_ The data uses the L11 format.
threshold
Units: Dimensionless, this register contains a coefficient.
MFR_COMMON
This command returns status information for the share-clock pin (SHARE_CLK) and the write-protect pin (WP).
MFR_COMMON Data Contents
BIT(S)
b[7:2]
b[1]
SYMBOL
OPERATION
Reserved
Read only, always returns ±s
Returns status of share-clock pin
1: Share-clock pin is being held low
±: Share-clock pin is active
Returns status of write-protect pin
1: Write-protect pin is high
±: Write-protect pin is low
Mfr_common_
share_clk
b[±]
Mfr_common_
write_protect
MFR_SPARE0
This 16-bit wide register can be used to store miscellaneous information. The contents of this register may be stored
and recalled from EEPROM using the STORE_USER_ALL and RESTORE_USER_ALL commands, respectively.
MFR_SPARE2
These 16-bit wide, paged registers can be used to store miscellaneous information. The contents of these registers may
bestoredandrecalledfromEEPROMusingtheSTORE_USER_ALLandRESTORE_USER_ALLcommands, respectively.
2978fc
53
LTC2978
PMBus COMMAND DESCRIPTION
MFR_VOUT_MIN
This command returns the minimum ADC measured value of the channel’s output voltage. This register is reset to
±xFFFF (7.999) when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
When odd channels are configured to measure current, this command is not supported. Updates are disabled when
undervoltage detection is disabled.
MFR_VOUT_MIN Data Contents
BIT(S)
SYMBOL
OPERATION
b[1ꢀ:±]
Mfr_vout_min
The data uses the L16 format.
Units: V.
MFR_VIN_MIN
This command returns the minimum ADC measured value of the input voltage. This register is reset to ±x7BFF
2ꢀ
(approximately 2 ) when the LTC2978 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
Updates are disabled when unit is off for insufficient input voltage.
MFR_VIN_MIN Data Contents
BIT(S)
SYMBOL
OPERATION
b[1ꢀ:±]
Mfr_vin_min
The data uses the L11 format.
Units: V.
MFR_TEMPERATURE_MIN
This command returns the minimum ADC measured value of junction temperature in °C as determined by the LTC2978’s
2ꢀ
internal temperature sensor. This register is reset to ±x7BFF (approximately 2 ) when the LTC2978 emerges from
power-on reset or when a CLEAR_FAULTS command is executed.
MFR_TEMPERATURE_MIN Data Contents
BIT(S) SYMBOL
OPERATION
b[1ꢀ:±] Mfr_temperature_min The data uses the L11 format.
Units: °C.
FAULT LOG OPERATION
A conceptual diagram of the fault log is shown in Figure 13. The fault log provides black box capability to the LTC2978.
During normal operation, the contents of the status registers, the output voltage/current readings, temperature readings
as well as peak and min values of these quantities are stored in a continuously updated buffer in RAM. You can think
of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are written into EEPROM
for nonvolatile storage. The EEPROM fault log is then locked. The part can be powered down with the fault log being
available for reading at a later time.
2978fc
54
LTC2978
PMBus COMMAND DESCRIPTION
8
ADC READINGS
CONTINUOUSLY
FILL BUFFER
TIME OF FAULT
TRANSFER TO
EEPROM AND
LOCK
.
.
.
.
.
.
RAM 255 BYTES
EEPROM 255 BYTES
AFTER FAULT
READ FROM
EEPROM AND
LOCK BUFFER
2978 F13
Figure 13. Fault Log Conceptual Diagram
MFR_FAULT_LOG_STORE
This command allows the user to transfer data from the RAM buffer to EEPROM.
MFR_FAULT_LOG_RESTORE
This command allows the user to transfer a copy of the fault-log data from the EEPROM to the RAM buffer. After a
restore the RAM buffer is locked until a successful Mfr_fault_log read.
MFR_FAULT_LOG_CLEAR
This command initializes the EEPROM block reserved for fault logging. Any previous fault log stored in EEPROM will
be erased by this operation.
MFR_FAULT_LOG_STATUS
Read only. This register is used to manage fault log events.
Mfr_fault_log_status_eepromissetafteraMFR_FAULT_LOG_STOREcommandorafaulted-offeventtriggersatransfer
of the fault log from RAM to EEPROM. This bit is cleared by a MFR_FAULT_LOG_CLEAR command.
Mfr_fault_log_status_ram is set after a MFR_FAULT_LOG_RESTORE to indicate that the data in the RAM has been
restored from EEPROM and not yet read using a MFR_FAULT_LOG command. This bit is cleared only by a successful
execution of an MFR_FAULT_LOG command.
MFR_FAULT_LOG_STATUS Data Contents
BIT(S) SYMBOL
OPERATION
b[1] Mfr_fault_log_status_ram
Fault log RAM status:
±: The fault log RAM allows updates.
1: The fault log RAM is locked until the next Mfr_fault_log read.
b[±] Mfr_fault_log_status_eeprom Fault log EEPROM status:
±: The transfer of the fault log RAM to the EEPROM is enabled.
1: The transfer of the fault log RAM to the EEPROM is inhibited.
2978fc
55
LTC2978
PMBus COMMAND DESCRIPTION
MFR_FAULT_LOG
Table 2. Data Block Contents
DATA
BYTE* DESCRIPTION
Read only. This 2±4±-bit data block contains a copy of
the RAM buffer fault log. The RAM buffer is continuously
updated after each ADC conversion as long as Mfr_fault_
log_status_ramisclear.WithMfr_config_fault_log_en=1
and Mfr_fault_log_status_eeprom = ±, the RAM buffer is
transferredtoEEPROMwheneveranLTC2978faultcauses
a channel to latch off or a MFR_FAULT_LOG_STORE com-
mand is received. Mfr_fault_log_status_eeprom is set
high after the RAM buffer is transferred to EEPROM and
not cleared until a Mfr_fault_log_clear is received, even if
the LTC2978 is reset or powered down. Fault log EEPROM
transfers are not initiated as a result of Status_mfr_dis-
charge, Status_mfr_fault1_in or Status_mfr_fault±_in
events. During a Mfr_fault_log read, data is returned as
defined by the following table. The fault log data is parti-
tioned into two sections. The first section is referred to as
the preamble and contains the Position-last pointer, time
information and peak and minimum values. The second
section contains a chronological record of telemetry and
requires Position-last for proper interpretation. The fault
log stores approximately 1 to 2 seconds of telemetry. To
prevent timeouts during block reads, it is recommended
that MFR_CONFIG_ALL_LTC2978 b[1] be set to 1.
Position_last[7:±]
±
Position of fault log pointer
when fault occurred.
SharedTime[7:±]
SharedTime[1ꢀ:8]
1
2
3
4
ꢀ
6
7
8
9
41-bit share-clock counter
value when fault occurred.
Counter LSB is in 2±±µs
increments. This counter is
cleared at power-up or after
the LTC2978 is reset
SharedTime[23:16]
SharedTime[31:24]
SharedTime[39:32]
SharedTime[4±]
Mfr_vout_peak±[7:±]
Mfr_vout_peak±[1ꢀ:8]
Mfr_vout_min±[7:±]
Mfr_vout_min±[1ꢀ:8]
Mfr_vout_peak1[7:±]
Mfr_vout_peak1[1ꢀ:8]
Mfr_vout_min1[7:±]
Mfr_vout_min1[1ꢀ:8]
Mfr_vin_peak[7:±]
1±
11
12
13
14
1ꢀ
16
17
18
19
2±
21
22
23
24
2ꢀ
26
27
28
29
3±
31
32
33
34
3ꢀ
36
37
38
39
4±
41
42
Mfr_vin_peak[1ꢀ:8]
Mfr_vin_min[7:±]
Mfr_vin_min[1ꢀ:8]
Mfr_vout_peak2[7:±]
Mfr_vout_peak2[1ꢀ:8]
Mfr_vout_min2[7:±]
Mfr_vout_min2[1ꢀ:8]
Mfr_vout_peak3[7:±]
Mfr_vout_peak3[1ꢀ:8]
Mfr_vout_min3[7:±]
Mfr_vout_min3[1ꢀ:8]
Mfr_temp_peak[7:±]
Mfr_temp_peak[1ꢀ:8]
Mfr_ temp_min[7:±]
Mfr_ temp_min[1ꢀ:8]
Mfr_vout_peak4[7:±]
Mfr_vout_peak4[1ꢀ:8]
Mfr_vout_min4[7:±]
Mfr_vout_min4[1ꢀ:8]
Mfr_vout_peakꢀ[7:±]
Mfr_vout_peakꢀ[1ꢀ:8]
Mfr_vout_minꢀ[7:±]
Mfr_vout_minꢀ[1ꢀ:8]
Mfr_vout_peak6[7:±]
Mfr_vout_peak6[1ꢀ:8]
Mfr_vout_min6[7:±]
Mfr_vout_min6[1ꢀ:8]
2978fc
56
LTC2978
PMBus COMMAND DESCRIPTION
Table 2. Data Block Contents
Table 3. Interpreting Cyclical Loop
DATA
BYTE* DESCRIPTION
POSITION
17
DATA
Read_vout3[1ꢀ:8]
Status_vout3
Mfr_vout_peak7[7:±]
Mfr_vout_peak7[1ꢀ:8]
Mfr_vout_min7[7:±]
Mfr_vout_min7[1ꢀ:8]
43
44
4ꢀ
46
18
19
2±
21
22
23
Status_mfr3
Read_temperature_1[7:±]
Read_temperature_1[1ꢀ:8]
Status_temp
47 bytes for preamble
Fault_log [Position_last]
Fault_log
47
48
Reserved
.
.
.
24
2ꢀ
26
Read_vout4[7:±]
Read_vout4[1ꢀ:8]
Status_vout4
27
28
29
3±
Status_mfr4
Fault_log
Reserved
237
238-2ꢀ4
Last Valid Byte
Read_voutꢀ[7:±]
Read_voutꢀ[1ꢀ:8]
Status_voutꢀ
Number of loops
(238-47)/4± = 4.8
*Note: PMBus data byte numbers start at 1 rather than ±. Position_last is the
first byte returned after BYTE COUNT = OxFF. See block read protocol.
31
32
33
34
3ꢀ
36
37
38
Status_mfrꢀ
Read_vout6[7:±]
Read_vout6[1ꢀ:8]
Status_vout6
Thedatareturnedbetweenbytes47and237oftheprevious
table is interpreted using Position_last and the following
table. The key to identifying byte 47 is to locate the DATA
corresponding to POSITION = Position_last in the next
table. Subsequent bytes are identified by decrementing
the value of POSITION. For example: If Position_last = 9
then the first data returned in byte position 47 of a block
readisRead_vin[1ꢀ:8]followedbyRead_vin[7:±]followed
by Status_mfr of page 1. See Table 3.
Status_mfr6
Read_vout7[7:±]
Read_vout7[1ꢀ:8]
Status_vout7
Status_mfr7
Total Bytes =4±
39
The following table fully decodes a sample fault log read
to help clarify the cyclical nature of the operation.
MFR_FAULT_LOG DATA BLOCK CONTENTS
PREAMBLE INFORMATION
Table 3. Interpreting Cyclical Loop
POSITION
DATA
±
1
2
3
4
ꢀ
6
7
8
Read_vout±[7:±]
Read_vout±[1ꢀ:8]
Status_vout±
Status_mfr±
Read_vout1[7:±]
Read_vout1[1ꢀ:8]
Status_vout1
Status_mfr1
BYTE
BYTE
NUMBER NUMBER
DECIMAL
HEX
DATA
DESCRIPTION
±
±±
Position_last[7:±] = 9 Position of
Fault-Log
Pointer When
Fault Occured.
1
±1
SharedTime[7:±]
41-Bit Share-
Clock Counter
Value When
Fault Occurred.
Counter LSB
Is in 2±±µs
Read_vin[7:±]
Read_vin[1ꢀ:8]
Status_vin
9
1±
11
12
13
14
1ꢀ
16
Reserved
Increments.
Read_vout2[7:±]
Read_vout2[1ꢀ:8]
Status_vout2
Status_mfr2
2
3
4
±2
±3
±4
SharedTime[1ꢀ:8]
SharedTime[23:16]
SharedTime[31:24]
Read_vout3[7:±]
2978fc
57
LTC2978
PMBus COMMAND DESCRIPTION
BYTE
BYTE
BYTE
BYTE
NUMBER NUMBER
NUMBER NUMBER
DECIMAL
ꢀ
HEX
±ꢀ
±6
±7
±8
±9
±A
±B
±C
±D
±E
±F
1±
11
12
13
14
1ꢀ
16
17
18
19
1A
1B
1C
1D
1E
1F
2±
21
22
23
24
2ꢀ
26
27
28
29
2A
2B
DATA
DESCRIPTION
DECIMAL
HEX
DATA
DESCRIPTION
SharedTime[39:32]
SharedTime[4±]
44
4ꢀ
46
2C
Mfr_vout_peak7[1ꢀ:8]
Mfr_vout_min7[7:±]
6
2D
2E
7
Mfr_vout_peak±[7:±]
Mfr_vout_peak±[1ꢀ:8]
Mfr_vout_min±[7:±]
Mfr_vout_min±[1ꢀ:8]
Mfr_vout_peak1[7:±]
Mfr_vout_peak1[1ꢀ:8]
Mfr_vout_min1[7:±]
Mfr_vout_min1[1ꢀ:8]
Mfr_vin_peak[7:±]
Mfr_vout_min7[1ꢀ:8] End of Preamble
8
CYCLICAL DATA LOOPS
LOOP
BYTE
9
BYTE
BYTE
1±
11
12
13
14
1ꢀ
16
17
18
19
2±
21
22
23
24
2ꢀ
26
27
28
29
3±
31
32
33
34
3ꢀ
36
37
38
39
4±
41
42
43
NUMBER NUMBER NUMBER
40 BYTES PER
DECIMAL
HEX
DECIMAL
DATA LOOP 0
Read_vin[1ꢀ:8]
Read_vin[7:±]
Status_mfr1
LOOP
47
2F
9
8
7
6
ꢀ
4
3
2
1
±
Position_last
48
3±
31
32
33
34
3ꢀ
36
37
38
49
ꢀ±
Status_vout1
Mfr_vin_peak[1ꢀ:8]
Mfr_vin_min[7:±]
ꢀ1
Read_vout1[1ꢀ:8]
Read_vout1[7:±]
Status_mfr±
ꢀ2
Mfr_vin_min[1ꢀ:8]
Mfr_vout_peak2[7:±]
Mfr_vout_peak2[1ꢀ:8]
Mfr_vout_min2[7:±]
Mfr_vout_min2[1ꢀ:8]
Mfr_vout_peak3[7:±]
Mfr_vout_peak3[1ꢀ:8]
Mfr_vout_min3[7:±]
Mfr_vout_min3[1ꢀ:8]
Mfr_temp_peak[7:±]
Mfr_temp_peak[1ꢀ:8]
Mfr_ temp_min[7:±]
Mfr_ temp_min[1ꢀ:8]
Mfr_vout_peak4[7:±]
Mfr_vout_peak4[1ꢀ:8]
Mfr_vout_min4[7:±]
Mfr_vout_min4[1ꢀ:8]
Mfr_vout_peakꢀ[7:±]
Mfr_vout_peakꢀ[1ꢀ:8]
Mfr_vout_minꢀ[7:±]
Mfr_vout_minꢀ[1ꢀ:8]
Mfr_vout_peak6[7:±]
Mfr_vout_peak6[1ꢀ:8]
Mfr_vout_min6[7:±]
Mfr_vout_min6[1ꢀ:8]
Mfr_vout_peak7[7:±]
ꢀ3
ꢀ4
Status_vout±
ꢀꢀ
Read_vout±[1ꢀ:8]
Read_vout±[7:±]
ꢀ6
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
HEX
39
3A
3B
3C
3D
3E
3F
DECIMAL
DATA LOOP 1
Status_mfr7
ꢀ7
39
ꢀ8
38
Status_vout7
ꢀ9
37
Read_vout7[1ꢀ:8]
Read_vout7[7:±]
Status_mfr6
6±
36
61
3ꢀ
62
34
Status_vout6
63
33
Read_vout6[1ꢀ:8]
Read_vout6[7:±]
Status_mfrꢀ
64
4±
41
42
43
44
4ꢀ
46
47
48
49
4A
32
6ꢀ
31
66
3±
Status_voutꢀ
67
29
Read_voutꢀ[1ꢀ:8]
Read_voutꢀ[7:±]
Status_mfr4
68
28
69
27
7±
26
Status_vout4
71
2ꢀ
Read_vout4[1ꢀ:8]
Read_vout4[7:±]
Reserved
72
24
73
23
74
22
Status_temp
2978fc
58
LTC2978
PMBus COMMAND DESCRIPTION
LOOP
LOOP
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
HEX
DECIMAL
DATA LOOP 1
DECIMAL
HEX
6D
6E
6F
DECIMAL
DATA LOOP 2
Status_mfr4
7ꢀ
4B
21
Read_
temperature_1[1ꢀ:8]
1±9
27
26
2ꢀ
24
23
22
21
11±
Status_vout4
Read_vout4[1ꢀ:8]
Read_vout4[7:±]
Reserved
76
4C
2±
Read_
temperature_1[7:±]
111
112
7±
71
72
73
77
78
79
8±
81
82
83
84
8ꢀ
86
87
88
89
9±
91
92
93
94
9ꢀ
96
4D
4E
4F
ꢀ±
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀꢀ
ꢀ6
ꢀ7
ꢀ8
ꢀ9
ꢀA
ꢀB
ꢀC
ꢀD
ꢀE
ꢀF
6±
19
18
17
16
1ꢀ
14
13
12
11
1±
9
Status_mfr3
113
Status_vout3
114
Status_temp
Read_vout3[1ꢀ:8]
Read_vout3[7:±]
Status_mfr2
11ꢀ
Read_temperature_
1[1ꢀ:8]
116
74
2±
Read_temperature_
1[7:±]
Status_vout2
Read_vout2[1ꢀ:8]
Read_vout2[7:±]
Reserved
117
118
119
12±
121
122
123
124
12ꢀ
126
127
128
129
13±
131
132
133
134
13ꢀ
136
7ꢀ
76
77
78
79
7A
7B
7C
7D
7E
7F
8±
81
82
83
84
8ꢀ
86
87
88
19
18
17
16
1ꢀ
14
13
12
11
1±
9
Status_mfr3
Status_vout3
Read_vout3[1ꢀ:8]
Read_vout3[7:±]
Status_mfr2
Status_vin
Read_vin[1ꢀ:8]
Read_vin[7:±]
Status_mfr1
8
Status_vout2
7
Read_vout2[1ꢀ:8]
Read_vout2[7:±]
Reserved
6
Status_vout1
ꢀ
Read_vout1[1ꢀ:8]
Read_vout1[7:±]
Status_mfr±
4
Status_vin
3
Read_vin[1ꢀ:8]
Read_vin[7:±]
Status_mfr1
2
Status_vout±
8
1
Read_vout±[1ꢀ:8]
Read_vout±[7:±]
7
±
6
Status_vout1
ꢀ
Read_vout1[1ꢀ:8]
Read_vout1[7:±]
Status_mfr±
LOOP
BYTE
4
BYTE
BYTE
3
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
2
Status_vout±
DECIMAL
HEX
61
62
63
64
6ꢀ
66
67
68
69
6A
6B
6C
DECIMAL
DATA LOOP 2
Status_mfr7
1
Read_vout±[1ꢀ:8]
Read_vout±[7:±]
97
39
±
98
38
Status_vout7
99
37
Read_vout7[1ꢀ:8]
Read_vout7[7:±]
Status_mfr6
LOOP
BYTE
1±±
1±1
1±2
1±3
1±4
1±ꢀ
1±6
1±7
1±8
36
BYTE
BYTE
3ꢀ
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
34
Status_vout6
DECIMAL
HEX
DECIMAL
DATA LOOP 3
Status_mfr7
33
Read_vout6[1ꢀ:8]
Read_vout6[7:±]
Status_mfrꢀ
137
89
39
38
37
36
3ꢀ
32
138
8A
8B
8C
8D
Status_vout7
31
139
Read_vout7[1ꢀ:8]
Read_vout7[7:±]
Status_mfr6
3±
Status_voutꢀ
14±
29
Read_voutꢀ[1ꢀ:8]
Read_voutꢀ[7:±]
141
28
2978fc
59
LTC2978
PMBus COMMAND DESCRIPTION
LOOP
LOOP
BYTE
BYTE
BYTE
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
142
143
144
14ꢀ
146
147
148
149
1ꢀ±
1ꢀ1
1ꢀ2
1ꢀ3
1ꢀ4
1ꢀꢀ
HEX
8E
8F
DECIMAL
DATA LOOP 3
Status_vout6
DECIMAL
177
178
179
18±
181
182
183
184
18ꢀ
186
187
188
189
19±
191
192
193
194
19ꢀ
HEX
B1
B2
B3
B4
Bꢀ
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
C±
C1
C2
C3
DECIMAL
DATA LOOP 4
Status_mfr7
34
39
33
Read_vout6[1ꢀ:8]
Read_vout6[7:±]
Status_mfrꢀ
38
Status_vout7
9±
91
92
93
94
9ꢀ
96
97
98
99
9A
9B
32
37
Read_vout7[1ꢀ:8]
Read_vout7[7:±]
Status_mfr6
31
36
3±
Status_voutꢀ
3ꢀ
29
Read_voutꢀ[1ꢀ:8]
Read_voutꢀ[7:±]
Status_mfr4
34
Status_vout6
28
33
Read_vout6[1ꢀ:8]
Read_vout6[7:±]
Status_mfrꢀ
27
32
26
Status_vout4
31
2ꢀ
Read_vout4[1ꢀ:8]
Read_vout4[7:±]
Reserved
3±
Status_voutꢀ
24
29
Read_voutꢀ[1ꢀ:8]
Read_voutꢀ[7:±]
Status_mfr4
23
28
22
Status_temp
27
21
Read_temperature_
1[1ꢀ:8]
26
Status_vout4
2ꢀ
Read_vout4[1ꢀ:8]
Read_vout4[7:±]
Reserved
1ꢀ6
9C
2±
Read_temperature_
1[7:±]
24
23
1ꢀ7
1ꢀ8
1ꢀ9
16±
161
162
163
164
16ꢀ
166
167
168
169
17±
171
172
173
174
17ꢀ
176
9D
9E
9F
19
18
17
16
1ꢀ
14
13
12
11
1±
9
Status_mfr3
22
Status_temp
Status_vout3
21
Read_temperature_
1[1ꢀ:8]
Read_vout3[1ꢀ:8]
Read_vout3[7:±]
Status_mfr2
A±
A1
A2
A3
A4
Aꢀ
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B±
196
C4
2±
Read_temperature_
1[7:±]
Status_vout2
197
198
199
2±±
2±1
2±2
2±3
2±4
2±ꢀ
2±6
2±7
2±8
2±9
21±
211
Cꢀ
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D±
D1
D2
D3
19
18
17
16
1ꢀ
14
13
12
11
1±
9
Status_mfr3
Read_vout2[1ꢀ:8]
Read_vout2[7:±]
Reserved
Status_vout3
Read_vout3[1ꢀ:8]
Read_vout3[7:±]
Status_mfr2
Status_vin
Read_vin[1ꢀ:8]
Read_vin[7:±]
Status_mfr1
Status_vout2
Read_vout2[1ꢀ:8]
Read_vout2[7:±]
Reserved
8
7
6
Status_vout1
ꢀ
Read_vout1[1ꢀ:8]
Read_vout1[7:±]
Status_mfr±
Status_vin
4
Read_vin[1ꢀ:8]
Read_vin[7:±]
Status_mfr1
3
8
2
Status_vout±
7
1
Read_vout±[1ꢀ:8]
Read_vout±[7:±]
6
Status_vout1
Read_vout1[1ꢀ:8]
±
ꢀ
2978fc
60
LTC2978
PMBus COMMAND DESCRIPTION
LOOP
RESERVED BYTES
BYTE
BYTE
BYTE
238
EE
±x±±
Bytes EE - FE
Return ±x±± But
Must Be Read
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
HEX
D4
Dꢀ
D6
D7
D8
DECIMAL
DATA LOOP 4
Read_vout1[7:±]
Status_mfr±
212
4
3
2
1
±
239
24±
241
242
243
244
24ꢀ
246
247
248
249
2ꢀ±
2ꢀ1
2ꢀ2
2ꢀ3
2ꢀ4
EF
F±
F1
F2
F3
F4
Fꢀ
F6
F7
F8
F9
FA
FB
FC
FD
FE
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
±x±±
213
214
Status_vout±
21ꢀ
Read_vout±[1ꢀ:8]
Read_vout±[7:±]
216
LOOP
BYTE
BYTE
BYTE
NUMBER NUMBER NUMBER
40 BYTES PER
LOOP
DECIMAL
217
218
219
22±
221
222
223
224
22ꢀ
226
227
228
229
23±
231
232
233
234
23ꢀ
HEX
D9
DA
DB
DC
DD
DE
DF
E±
E1
E2
E3
E4
Eꢀ
E6
E7
E8
E9
EA
EB
DECIMAL
DATA LOOP 5
Status_mfr7
39
38
Status_vout7
37
Read_vout7[1ꢀ:8]
Read_vout7[7:±]
Status_mfr6
36
3ꢀ
34
Status_vout6
33
Read_vout6[1ꢀ:8]
Read_vout6[7:±]
Status_mfrꢀ
32
Use One Block
Read Command
to Read 2ꢀꢀ
Bytes Total,
from ±x±± to
±xFE
31
3±
Status_voutꢀ
29
Read_voutꢀ[1ꢀ:8]
Read_voutꢀ[7:±]
Status_mfr4
28
27
26
Status_vout4
2ꢀ
Read_vout4[1ꢀ:8]
Read_vout4[7:±]
Reserved
24
23
22
Status_temp
21
Read_temperature_
1[1ꢀ:8]
236
237
EC
ED
2±
19
Read_temperature_
1[7:±]
Status_mfr3
Last Valid Fault
Log Byte
2978fc
61
LTC2978
APPLICATIONS INFORMATION
OVERVIEW
tor converts V
down to 3.3V which drives all of the
PWR
internal circuitry of the LTC2978.
The LTC2978 is a power management IC that is capable
of sequencing, margining, trimming, supervising output
voltage for OV/UV conditions, providing fault manage-
ment, and voltage read back for eight DC/DC converters.
Input voltage and LTC2978 junction temperature read
back are also available. Odd numbered channels can be
configured to read back sense resistor voltages. Multiple
LTC2978s can be synchronized to operate in unison using
theSHARE_CLK,FAULTBandCONTROLpins.TheLTC2978
utilizes a PMBus compliant interface and command set.
Alternatively, power from an external 3.3V supply may be
applied directly to the V
age between 3.13V and 3.47V. Tie V
pins 16 and 17 using a volt-
DD33
to V
pins.
PWR
DD33
See Figure 1ꢀ. All functionality is available when using
this alternate power method. The higher voltages needed
for the V
pins and bias for the V
pins are
OUT_EN[±:3]
SENSE
charge pumped from V
.
DD33
SETTING COMMAND REGISTER VALUES
The command register settings described herein are for
the purpose of understanding and software development
in a host processor. In actual practice, the LTC2978 can
be completely configured for standalone operation with
POWERING THE LTC2978
The LTC2978 can be powered two ways. The first method
requires that a voltage between 4.ꢀV and 1ꢀV be applied
2
to the V
pin. See Figure 14. An internal linear regula-
theLTCUSBtoI C/SMBus/PMBuscontrollerandsoftware
PWR
GUI using intuitive menu driven objects.
4.5V < V
< 15V
PWR
V
V
IN_SNS
SEQUENCE, SERVO, MARGIN AND RESTART
OPERATIONS
PWR
0.1µF
0.1µF
0.1µF
V
V
V
DD33
DD33
DD25
LTC2978
GND
Command Units On or Off
Three control parameters determine how a particular
channel is turned on and off. The CONTROL pins, the
OPERATION command and the value of the input voltage
*SOME DETAILS
OMITTED FOR CLARITY
2978 F14
measured at the V
pin (V ). In all cases, V must
IN_SNS
IN IN
Figure 14. Powering LT2978 Directly from an Intermediate Bus
exceed VIN_ON in order to enable a start. When V drops
IN
belowVIN_OFFanimmediateOFFofallchannelswillresult.
Refer to the OPERATION section in the data sheet for a
detailed description of the ON_OFF_CONFIG command.
Some examples of typical ON/OFF configurations are:
1. ADC/DCconvertermaybeconfiguredtoturnonanytime
EXTERNAL 3.3V
0.1µF
V
PWR
V
V
V
DD33
DD33
DD25
LTC2978
GND
V exceeds VIN_ON.
IN
2. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command.
0.1µF
*SOME DETAILS
OMITTED FOR CLARITY
2978 F15
3. A DC/DC converter may be configured to turn on only
via the CONTROL pin.
Figure 15. Powering LTC2978 from External 3.3V Supply
4. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command and the
CONTROL pin is asserted.
2978fc
62
LTC2978
APPLICATIONS INFORMATION
On Sequencing
totheMFR_CONFIG_LTC2978commandfordetailsonhow
to configure the output voltage servo.
The TON_DELAY command sets the amount of time that
a channel will wait following the start of an ON sequence
Servo Modes
before its V
pin will enable a DC/DC converter. Once
OUT_EN
The ADC, DAC and internal processor comprise a digital
servo loop that can be configured to operate in several
usefulmodes.Theservotargetreferstothedesiredoutput
voltage.
the DC/DC converter has been enabled, the TON_RISE
command determines the amount of time the LTC2978
waits before soft connecting the V
output and ser-
DACPn
voing the DC/DC converter output to VOUT_COMMAND.
The TON_MAX_FAULT_LIMIT command determines the
amountoftimeaftertheDC/DCconverterhasbeenenabled
that an undervoltage condition will be tolerated before a
fault occurs. If a TON_MAX_FAULT occurs, the channel
can be configured to disable the DC/DC converter and
propagatethefaulttootherchannelsusingthebidirectional
FAULTBpins.Figure16showsatypicalon-sequenceusing
the CONTROL pin.
Continuous/noncontinuous trim mode. MFR_CONFIG_
LTC2978 b[7]. In continuous trim mode, the servo will
update the DAC in a closed loop fashion each time it
takes a V
reading. The update rate is determined by
OUT
the time it takes to step through the ADC MUX which is
typically 1±±ms. See Electrical Characteristics Table Note
6. In noncontinuous trim mode, the servo will drive the
DAC until the ADC measures the output voltage desired
and then stop updating the DAC.
On State Operation
Noncontinuous servo on warn mode. MFR_CONFIG_
LTC2978b[7]=±, b[6]=1. Wheninnoncontinuousmode,
the LTC2978 can additionally retrim (reservo) the output if
the output drifts beyond the OV or UV warn limits.
Once a channel has reached the ON state, the OPERATION
command can be used to command the DC/DC converter’s
output to margin high, margin low, or return to a nominal
outputvoltageindicatedbyVOUT_COMMAND.Theuseralso
hastheoptionofconfiguringachanneltocontinuouslytrim
theoutputoftheDC/DCconvertertotheVOUT_COMMAND
DAC Modes
The DACs that drive the V
pins can operate in several
DACn
voltage, or the channel’s V
output can be placed in a
DACPn
useful modes. See MFR_CONFIG_LTC2978.
high impedance state thus allowing the DC/DC converter
output voltage to go to its nominal value, V . Refer
•ꢀ Softꢀ connect.ꢀ Usingꢀ theꢀ LTCꢀ patentedꢀ softꢀ connectꢀ
feature, the DAC output is driven to within 1 LSB of the
voltage at the DC/DC's feedback node before connect-
ing to avoid introducing transients on the output. This
mode is used when servoing the output voltage. During
start-up,theLTC2978waitsuntilTON_RISEhasexpired
before connecting the DAC. This is the most common
operating mode.
DCn(NOM)
V
CONTROL
V
OUT_EN
VOUT_0V_FAULT_LIMIT
V
OUT_COMMAND
DAC SOFT-CONNECTS
AND BEGINS
ADJUSTING OUTPUT
V
DC(NOM)
•ꢀ Disconnected.ꢀDACꢀoutputꢀisꢀhighꢀZ.
VOUT_UV_FAULT_LIMIT
V
OUT
•ꢀ DACꢀmanualꢀwithꢀsoftꢀconnect.ꢀNonꢀservoꢀmode.ꢀTheꢀ
DAC soft connects to the feedback node . The DAC code
isdriventomatchthevoltageatthefeedbacknode.After
connection, the DAC is moved by writing DAC codes to
the device.
2978 F16
TON_RISE
TON_DELAY
TON_MAX_FAULT_LIMIT
Figure 16. Typical On Sequence Using Control Pin
2978fc
63
LTC2978
APPLICATIONS INFORMATION
•ꢀ DACꢀmanualꢀwithꢀhardꢀconnect.ꢀNonꢀservoꢀmode.ꢀTheꢀ
DAC hard connects to the feedback node at the value
in MFR_DAC. After connection, the DAC is moved by
writing DAC codes to the device.
Automatic Restart Via MFR_RESTART_DELAY
Command and CONTROLn pin
An automatic restart sequence can be initiated by driving
the CONTROL pin to the off state for >1±μs then releas-
ing it. The automatic restart disables all V
pins
OUT_EN
Margining
that are mapped to a particular CONTROL pin for a time
period=MFR_RESTART_DELAYandthenstartsallDC-DC
Converters according to their respective TON_DELAYs.
The LTC2978 margins and trims the output of a DC/DC
converter by driving current into or out of the feedback
node or the trim pin. Preset limits for margining are stored
in the VOUT_MARGIN_HIGH/LOW registers. Margining
is actuated by writing the appropriate bits to the OPERA-
TION register.
(see Figure 17). V
pins are mapped to one of the
OUT_ENn
CONTROLpinsbytheMFR_CONFIG_LTC2978command.
This feature allows a host that is about to reset to restart
the power in a controlled manner after it has recovered.
Margining requires the DAC to be connected. Margin
requests that occur when the DAC is disconnected will
force the DAC to soft connect. When in the margin high/
low state, the DAC cannot be disconnected. The DAC can
only be disconnected from the ON state.
CONTROL
PIN BOUNCE
V
CONTROL
V
OUT_END
2978 F17
Off Sequencing
TOFF_DELAY0
MFR_RESTART_DELAY TON_DELAY0
An off sequence is initiated using the CONTROL pin or
the OPERATION command. The TOFF_DELAY command
determines the amount of time that elapses from the be-
Figure 17. Off Sequence with Automatic Restart
ginning of the off sequence until each channel’s V
OUT_EN
pin is pulled low thus disabling its DC/DC converter.
FAULT MANAGEMENT
V
OUT
Off Threshold Voltage
Output Overvoltage and Undervoltage Faults
The MFR_VOUT_DISCHARGE_THRESHOLD command
register allows the user to specify the OFF threshold that
the output voltage must decay below before the channel
can enter/re-enter the ON state. The OFF threshold voltage
is specified by multiplying MFR_VOUT_DISCHARGE_
THRESHOLD and VOUT_COMMAND. In the event that an
output voltage has not decayed below its OFF threshold
before attempting to enter the ON state, the channel will
continue to be held off, the appropriate bit is set in the
STATUS_MFR_SPECIFICregister, andtheALERTBpinwill
be asserted low. When the output voltage has decayed
belowitsOFFthreshold,thechannelcanentertheONstate.
ThehighspeedvoltagesupervisorOVandUVfaultthresh-
oldsareconfiguredusingtheVOUT_OV_FAULT_LIMITand
VOUT_UV_FAULT_LIMIT commands, respectively. The
VOUT_OV_FAULT_RESPONSEandVOUT_UV_FAULT_RE-
SPONSE commands determine the responses to OV/
UV faults. Fault responses can range from disabling the
DC/DC converter immediately, waiting to see if the fault
condition persists for some interval before disabling
the DC/DC converter, or allowing the DC/DC converter
to continue operating in spite of the fault. If a DC/DC
converter is disabled, the LTC2978 can be configured to
retry or latch-off. The retry interval is specified using the
2978fc
64
LTC2978
APPLICATIONS INFORMATION
Configuring the V
Output
MFR_RETRY_DELAY command. Latched faults are reset
bytogglingtheCONTROLpin,usingtheOPERATIONcom-
mand, or removing and reapplying the bias voltage to the
IN_EN
The V
output may be used to disable the interme-
IN_EN
diate bus voltage in the event of an output OV or UV
fault. Use the MFR_VINEN_OV_FAULT_RESPONSE and
MFR_VINEN_UV_FAULT_RESPONSE registers to config-
V
pin. All fault and warning conditions result in the
IN_SNS
ALERTB pin being asserted low and the corresponding
bits being set in the status registers. The CLEAR_FAULTS
command resets the contents of the status registers and
deasserts the ALERTB output.
ure the V
pin to assert low in response to VOUT_OV/
IN_EN
UV fault conditions. The V
output will stop pulling
IN_EN
low when the LTC2978 is commanded to re-enter the ON
state following a faulted-off condition.
Output Overvoltage and Undervoltage Warnings
Acharge-pumpedꢀµApull-upto12Visalsoavailableonthe
OV and UV warning threshold voltages are processed
by the LTC2978’s ADC. These thresholds are set by the
VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT
commands respectively. If a warning occurs, the corre-
spondingbitsaresetinthestatusregistersandtheALERTB
output is asserted low. Note that a warning will never
V
output. Refer to the MFR_CONFIG_ALL_LTC2978
IN_EN
register description in the OPERATION section for more
information.
Figure 18 shows an application circuit where the V
IN_EN
outputisusedtotriggeraSCRcrowbarontheintermediate
bus in order to protect the DC/DC converter’s load from a
catastrophic fault such as a stuck top gate.
cause a V
output pin to disable a DC/DC converter.
OUT_EN
R
Q1
SENSE
0.007Ω
Si4894BDY
V
IN
V
IN
<15V
C
BYPASS
V
V
OUT
IN_SNS
V
V
PWR
DACP0
DC/DC
CONVERTER
100Ω
68Ω
V
V
SENSE
GATE
LTC4210-3
SENSEP0
CC
0.1µF
LTC2978*
24.3k
V
LOAD
FB
ON
V
DACM0
0.01µF
TIMER GND
V
10k
SGND
SENSEM0
V
RUN/SS
0.22µF
OUT_EN0
GND
10k
0.01µF
2978 F18
2907
MCR12DC
4.99k
220Ω
0.1µF
BAT54
REFP
V
REFM
IN_EN
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
V
V
V
GND
DD33 DD33 DD25
0.1µF
0.1µF
Figure 18. LTC2978 Application Circuit with Crowbar Protection on Intermediate Bus
2978fc
65
LTC2978
APPLICATIONS INFORMATION
Mfr_faultb00_response, page = 0
Mfr_faultbz0_propagate_ch0
FAULTED_OFF
CHANNEL 0
EVENT PROCESSOR
PAGE = 0
FAULTB00
FAULTB01
Mfr_faultb01_response, page = 0
Mfr_faultbz1_propagate_ch0
Mfr_faultb00_response, page = 1
Mfr_faultb01_response, page = 1
Mfr_faultbz0_propagate_ch1
FAULTED_OFF
CHANNEL 1
EVENT PROCESSOR
PAGE = 1
Mfr_faultbz1_propagate_ch1
Mfr_faultb00_response, page = 2
Mfr_faultb01_response, page = 2
Mfr_faultbz0_propagate_ch2
FAULTED_OFF
CHANNEL 2
EVENT PROCESSOR
PAGE = 2
Mfr_faultbz1_propagate_ch2
Mfr_faultb00_response, page = 3
Mfr_faultb01_response, page = 3
Mfr_faultbz0_propagate_ch3
FAULTED_OFF
CHANNEL 3
EVENT PROCESSOR
PAGE = 3
Mfr_faultbz1_propagate_ch3
ZONE 0
ZONE 1
ZONE 0
ZONE 1
Mfr_faultb10_response, page = 4
Mfr_faultb11_response, page = 4
Mfr_faultbz0_propagate_ch4
FAULTED_OFF
CHANNEL 4
EVENT PROCESSOR
PAGE = 4
FAULTB10
FAULTB11
Mfr_faultbz1_propagate_ch4
Mfr_faultb10_response, page = 5
Mfr_faultb11_response, page = 5
Mfr_faultbz0_propagate_ch5
FAULTED_OFF
CHANNEL 5
EVENT PROCESSOR
PAGE = 5
Mfr_faultbz1_propagate_ch5
Mfr_faultb10_response, page = 6
Mfr_faultb11_response, page = 6
Mfr_faultbz0_propagate_ch6
FAULTED_OFF
CHANNEL 6
EVENT PROCESSOR
PAGE = 6
Mfr_faultbz1_propagate_ch6
Mfr_faultb10_response, page = 7
Mfr_faultb11_response, page = 7
Mfr_faultbz0_propagate_ch7
FAULTED_OFF
Mfr_faultbz1_propagate_ch7
CHANNEL 7
EVENT PROCESSOR
PAGE = 7
2978 F19
Figure 19. Channel Fault Management Block Diagram
2978fc
66
LTC2978
APPLICATIONS INFORMATION
Multichannel Fault Management
•ꢀꢀ AꢀFAULTBzn pin can also be asserted low by an external
driver in order to initiate an immediate off-sequence
after a 1±µs deglitch delay.
Multichannel fault management is handled using the
bidirectional FAULTBzn pins. The “z” designates the fault
zone which is either ± or 1. There are two fault zones in
the LTC2978. Each zone contains 4-channels. Figure 19
illustrates the connections between channels and the
FAULTBzn pins.
INTERCONNECT BETWEEN MULTIPLE LTC2978’S
Figure 2± shows how to interconnect the pins in a typical
multi-LTC2978 array.
•ꢀꢀ TheꢀMFR_FAULTBz0_PROPAGATEꢀcommandꢀactsꢀlikeꢀ
a programmable switch that allows faulted-off condi-
tions from a particular channel (PAGE) to propagate
to either FAULTBzn output in that channel’s zone. The
MFR_FAULTBzn_RESPONSEcommandcontrolssimilar
switches on the inputs to each channel that allow any
channeltoshutdowninresponsetoanycombinationof
the FAULTBzn pins within a zone. Channels responding
to a FAULTBzn pin pulling low will attempt a new start
sequencewhentheFAULTBznpininquestionisreleased
by the faulted channel.
•ꢀꢀ AllꢀV
lines should be tied together in a star type
IN_SNS
connection at the point where V is to be sensed.
IN
This will minimize timing errors for the case where the
ON_OFF_CONFIG is configured to start the LTC2978
based on V and ignore the CONTROL line and the
IN
OPERATION command. In multi-part applications that
are sensitive to timing differences, it is recommended
thattheVin_share_enablebitoftheMFR_CONFIG_ALL
register be set high in order to allow SHARE_CLK to
synchronize on/off sequencing in response to the
VIN_ON and VIN_OFF thresholds.
•ꢀꢀ Toꢀestablishꢀdependenciesꢀacrossꢀfaultꢀzones,ꢀtieꢀtheꢀ
fault pins together, e.g., FAULTB±1 to FAULTB1±. Any
channel can depend on any other. To disable all chan-
nels in response to any channel faulting off, short all
the FAULTBzn pins together, and set MFR_FAULTBzn_
PROPAGATE = ±x±1 and MFR_FAULTBzn_RESPONSE
= ±x±F for all channels.
•ꢀꢀ ConnectingꢀallꢀV
lines together will allow selected
IN_EN
faults on any DC/DC converter’s output in the array to
shut off a common input switch.
TO V OF
IN
DC/DCs
TO INPUT
SWITCH
TO HOST CONTROLLER
LTC2978 N-1
VIN_SNS
LTC2978 N
VIN_SNS
VIN_EN
VIN_EN
SDA
SCL
SDA
SCL
ALERTB
ALERTB
CONTROL0
CONTROL1
WDI/RESETB
FAULTB00
FAULTB01
FAULTB10
FAULTB11
SHARE_CLK
PWRGD
CONTROL0
CONTROL1
WDI/RESETB
FAULTB00
FAULTB01
FAULTB10
FAULTB11
SHARE_CLK
PWRGD
GND
GND
2978 F20
TO OTHER LTC2978s–10k EQUIV PULL-UP RECOMMENDED
ON EACH LINE EXCEPT SHARE_CLK (USE 5.49k)
Figure 20. Typical Connections Between Multiple LTC2978s
2978fc
67
LTC2978
APPLICATIONS INFORMATION
•ꢀꢀ ALERTBꢀ isꢀ typicallyꢀ oneꢀ lineꢀ inꢀ anꢀ arrayꢀ ofꢀ PMBusꢀ •ꢀꢀ PWRGDꢀreflectsꢀtheꢀstatusꢀofꢀtheꢀoutputsꢀthatꢀareꢀmappedꢀ
converters. The LTC2978 allows a rich combination of
faults and warnings to be propagated to the ALERTB
pin.
to it by the MFR_PWRGD_EN command. Figure 19
shows all the PWRGD pins connected together, but any
combination may be used. Note that the latency of the
PWRGD pin response may be in the range of 3±ms to
18ꢀms depending on ADC MUX settings. See Electrical
Characteristics Table Note 6.
•ꢀꢀ WDI/RESETBꢀcanꢀbeꢀusedꢀtoꢀputꢀtheꢀLTC2978ꢀinꢀtheꢀ
power-on reset state. Pull WDI/RESETB low for at least
t
to enter this state.
RESETB
A fast deassertion of PWRGD may be implemented by
•ꢀꢀ TheꢀFAULTBznlinescanbeconnectedtogethertocreate
fault dependencies. Figure 2± shows a configuration
where a fault on any FAULTBzn will pull all others low.
This is useful for arrays where it is desired to abort a
start-up sequence in the event any channel does not
come up (see Figure 21).
wire ANDing the V
pin with the PWRGD pin. When
IN_EN
the UV fault threshold is crossed, V
will pull low
IN_EN
if programmed to do so. See Figure 22.
V
CONTROLn
V
OUT0
TON_DELAY0
TON_DELAY1
V
V
OUT1
OUT2
TON_DELAY2
•
•
•
•
•
•
V
OUTn
TON_DELAYn
BUSSED
VFAULTBzn
PINS
2978 F21
TON_MAX_FAULT1
Figure 21. Aborted On Sequence Due to Channel 1 Short
V
IN_EN
4.7k
LTC2978
V
DD33
PWRGD
FAST PWRGD
DEASSERT
2978 F22
Figure 22. PWRGD Deassert
2978fc
68
LTC2978
APPLICATIONS INFORMATION
APPLICATION CIRCUITS
V
is the output voltage of the DC/DC converter
DC(NOM)
when the LTC2978’s V
pin is in a high impedance
DACP±
Trimming and Margining DC/DC Converters with
External Feedback Resistors
state. R1± is a function of R2±, V
, the voltage at
DC(NOM)
the feedback node (V ) when the loop is in regulation,
FB
and the feedback node’s input current (I ).
FB
Figure 23 shows a typical application circuit for trimming/
margining a power supply with an external feedback
R2± • VFB
R1± =
(1)
network. The V
and V
differential inputs
SENSEP±
SENSEM±
VDC(NOM) –IFB • R2± – V
FB
sense the load voltage directly, and a correction voltage
is developed between the V and V pins by the
DACP±
DACM±
is Kelvin connected
2. Solve for the value of R3± that yields the maximum
required DC/DC converter output voltage V
closed-loop servo algorithm. V
DACM±
.
DC(MAX)
to the point-of-load GND in order to minimize the effects
of load induced grounding errors. The V output
WhenV
is at its maximum voltage.
isat±V, theoutputoftheDC/DCconverter
DACP±
DACP±
is connected to the DC/DC converter’s feedback node
through resistor R3±. For this configuration, set b[±] in
MFR_CONFIG_LTC2978 = ±.
R2± • VFB
R3± ≤
(2)
VDC(MAX) – VDC(NOM)
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors
3. Solve for the minimum value of V
that’s needed
DACP±
to yield the minimum required DC/DC converter output
The following four-step procedure should be used to
calculate the resistor values required for the application
circuit shown in Figure 23.
voltage V
.
DC(MIN)
The DAC has two full-scale settings, 1.38V and 2.6ꢀV.
In order to select the appropriate full-scale setting,
calculate the minimum required V
voltage:
1. AssumevaluesforfeedbackresistorR2±andthenominal
output
DACP±(F/S)
DC/DC converter output voltage V
for R1±.
, and solve
DC(NOM)
R3±
R2±
VDACP±(F /S) > VDC(NOM) – VDC(MIN)
•
+ VFB
(
)
(3)
V
IN
V
V
IN
4.5V < V
< 15V
IBUS
V
V
PWR
IN_SNS
OUT
0.1µF
V
DACP0
0.1µF
R30
DC/DC
CONVERTER
V
V
V
V
SENSEP0
DD33
DD33
DD25
R20
R10
LTC2978*
V
LOAD
FB
V
DACM0
0.1µF
V
SGND
SENSEM0
V
RUN/SS
OUT_EN0
GND
2978 F23
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
Figure 23. Application Circuit for DC/DC Converters with External Feedback Resistors
2978fc
69
LTC2978
APPLICATIONS INFORMATION
4. Recalculate the minimum, nominal, and maximum
DC/DC converter output voltages and the resulting
margining resolution.
relationships between these resistors and the Δ5 change
in the output voltage of the DC/DC converter are typically
expressed as:
R2±
R1±
RTRIM • 50
VDC(NOM) = VFB • 1+
+ IFB •R2±
(4)
RTRIM_DOWN
=
–RTRIM
(8)
ΔDOWN
%
R2±
R3±
R2±
R3±
VDC(MIN) = VDC(NOM)
–
• V
– V
(ꢀ)
(6)
RTRIM_UP
=
(
)
FB
DACP±(F /S)
VDC • 100+ Δ %
(
)
50
VDC(MAX) = VDC(NOM)
+
• V
UP
FB
RTRIM
•
–
– 1
(9)
2 • VREF • ΔUP%
Δ %
UP
R2±
• VDACP±(F /S)
R3±
where R
is the resistance looking into the TRIM pin,
VRES
=
V/DAC LSB
(7)
TRIM
1±24
V
is the TRIM pin’s open-circuit output voltage and V
REF
DC
istheDC/DCconverter’snominaloutputvoltage.Δ 5and
UP
Δ
5 denote the percentage change in the converter’s
DOWN
Trimming and Margining DC/DC Converters with a
TRIM Pin
output voltage when margining up or down, respectively.
Figure 24 illustrates a typical application circuit for trim-
ming/margining the output voltage of a DC/DC converter
Two-Step Resistor and DAC Full-Scale Voltage
Selection Procedure for DC/DC Converters with a
TRIM Pin
with a TRIM Pin. The LTC2978’s V
pin connects to
DACP±
the TRIM pin through resistor R3±, and the V
pin
DACM±
The following two-step procedure should be used to cal-
culatetheresistorvalueforR3±andtherequiredfull-scale
DAC voltage (refer to Figure 24).
is connected to the converter’s point-of-load ground. For
this configuration, set the DAC polarity bit Mfr_config_
dac_pol in MFR_CONFIG_LTC2978 to 1.
1. Solve for R3±:
DC/DC converters with a TRIM pin are typically margined
high or low by connecting an external resistor between
50 – ΔDOWN
%
R30 ≤RTRIM
•
(10)
the TRIM pin and either the V
or V
pin. The
SENSEP
SENSEM
ΔDOWN
%
V
IN
V
V
IN
4.5V < V
< 15V
IBUS
+
OUT
V
V
IN_SNS
PWR
R30
0.1µF
TRIM
V
V
DACP0
0.1µF
+
V
V
V
V
SENSEP0
SENSE
DD33
DD33
DD25
DC/DC
LTC2978*
CONVERTER
LOAD
V
DACM0
0.1µF
–
V
V
SENSEM0
SENSE
ON/OFFB
GND
V
OUT_EN0
GND
2978 F24
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
Figure 24. Application Circuit for DC/DC Converters with Trim Pin
2978fc
70
LTC2978
APPLICATIONS INFORMATION
Measuring Current with Inductor DCR
2. Calculate the maximum required output voltage for
V
DACP±
:
Figure 26 shows the circuit for applications that require
DCR current sense. A second order RC filter is required
in these applications in order to minimize the ripple volt-
age seen at the current sense inputs. A value of 1kΩ
ΔUP%
VDAC ≥ 1+
• V
(11)
P0
REF
ΔDOWN
%
is suggested for R
and R
in order to minimize
CM1
CM2
Note: Not all DC/DC’s converters follow these trim equa-
tionsespeciallynewerbricks.ConsultLTCFieldApplication
Engineering.
gain errors due the current sense inputs’ internal resis-
tance. C should be selected to provide cancellation
CM1
of the zero created by the DCR and inductance, i.e.
ꢀ=ꢀL/(DCR•ꢀR ).C shouldbeselectedtoprovide
C
CM1
CM1
CM2
Measuring Current
a second stage corner frequency at < 1/1± of the DC/DC
converter’sswitchingfrequency.Inaddition,C needsto
Odd numbered ADC channels may be used to measure
supply current. Set the ADC to high resolution mode to
configure for current measuring and improve sensitivity.
Note that no OV or UV faults or warnings are reported in
thismode,buttelemetryisavailablefromtheREAD_VOUT
command using the 11-bit signed mantissa plus ꢀ-bit
signed exponent L11 data format. Set the MFR_CON-
FIG_LTC2978bitb[9]=1inordertoenablehighresmode.
CM2
be much smaller than C
loading of the filter’s first stage.
in order to prevent significant
CM1
R
CM
R
CM
V
V
SENSEP1
C
C
CM
LTC2978
CM
The V
pin will assert low in this mode and cannot
OUT_EN
SENSEM1
L
R
SNS
be used to control a DC/DC converter. The V
pin is also unavailable.
output
2978 F25
DACP
LOAD CURRENT
Measuring Current with a Sense Resistor
Figure 25. Sense Resistor Current Sensing Circuits
A circuit for measuring current with a sense resistor is
shown in Figure 2ꢀ. The balanced filter rejects both com-
mon mode and differential mode noise from the output of
theDC/DCconverter. Thefilterisplaceddirectlyacrossthe
sense resistor in series with the DC/DC converter’s induc-
tor. Note that the current sense inputs must be limited to
R
R
CM2
CM2
V
V
SENSEP1
C
C
CM2
LTC2978
C
CM1
C
CM1
CM2
SENSEM1
less than 6V with respect to ground. Select R and C
CM
CM
2978 F26
such that the filter’s corner frequency is < 1/1± the DC/DC
converter’sswitchingfrequency.Thiswillresultinacurrent
sense waveform that offers a good compromise between
the voltage ripple and the delay through the filter. A value
R
R
CM1
CM1
L
DCR
SWX0
Figure 26. Sense Resistor Current Sensing Circuits
1kΩ for R is suggested in order to minimize gain er-
CM
rors due to the current sense inputs’ internal resistance.
2978fc
71
LTC2978
APPLICATIONS INFORMATION
Single Phase Design Example
Measuring Multiphase Currents
As a design example for a DCR current sense application,
For current sense applications with more than one phase,
RC averaging may be employed. Figure 27 shows an
example of this approach for a 3-phase system with DCR
current sensing. The current sense waveforms are aver-
aged together prior to being applied to the second stage of
assume L = 2.2μH, DCR = 10mΩ, and F = 500kHz.
SW
Let R
= 1kΩ and solve for C
:
CM1
CM1
2.2µH
10mΩ • 1kΩ
C
≥
= 220nF
CM1
the filter consisting of R
and C . Because the R
CM2 CM2 CM1
resistors for the three phases are in parallel, the value of
must be multiplied by the number of phases. Also
R
Let R
SW
= 1kΩ. In order to get a second pole at
CM1
CM2
/10 = 50kHz:
note that since the DCRs are effectively in parallel, the
value for IOUT_CAL_GAIN will be equal to the inductor’s
DCR divided by the number of phases. Care should to be
taken in the layout of the multiphase inductors to keep the
PCB trace resistance from the DC side of each inductor to
the summing node balanced in order to provide the most
accurate results.
F
1
C
≅
= 3.18nF
CM2
2π• 50kHz • 1kΩ
Let C
CM1
= 3.3nF. Note that since C
is much less than
CM2
CM2
C
the loading effects of the second stage filter on the
matched first stage are not significant. Consequently, the
delay time constant through the filter for the current sense
waveform will be approximately 3μs.
Multiphase Design Example
Using the same values for inductance and DCR from
the previous design example, the value for R
will be
CM1
3kΩ for a three phase DC/DC converter if C
is left at
CM1
220nF. Similarly, the value for IOUT_CAL_GAIN will be
DCR/3 = 3.33mΩ.
SWX1
R
R
CM1
CM1
R
CM2
R
C
CM1
C
CM2
CM1
L
I
I
SENSEP
LTC2978
DCR
SENSEM
2978 F27
R
/3
CM1
R
CM2
DCR
DCR
C
CM1
C
CM2
L
L
TO LOAD
SWX2
SWX3
Figure 27. Multiphase DCR Current Sensing Circuits
2978fc
72
LTC2978
APPLICATIONS INFORMATION
Anti-aliasing Filter Considerations
while the VSENSEP1 input is tied to the REFP pin which
has a typical output voltage of 1.23V. The voltage divider
should be configured in order to present about 0.5V to the
voltage sense inputs when the negative supply reaches its
POWER_GOOD_ON threshold so that the current flowing
out of the VSENSEMn pin is minimized to ~1µA. The
relationship between the POWER_GOOD_ON register
value and the corresponding negative supply value can
be expressed as:
Noisy environments require an anti-aliasing filter on the
input to the LTC2978’s ADC. The R-C circuit shown in
Figure 28 is adequate for most situations. Keep R40 = R50
≤ 200Ω to minimize ADC gain errors, and select a value
for capacitors C10 and C20 that doesn’t add too much
additional response time to the OV/UV supervisor, e.g. τ
≅ 10µs (R = 100Ω, C = 0.10µF).
Sensing Negative Voltages
R2
R1
+1 – 1µA•R2
VEE = VREFP –(READ_VOUT) •
Figure 29 shows the LTC2978 sensing a negative power
supply (V ). The R1/R2 resistor divider translates the
EE
negativesupplyvoltagetotheLTC2978sVSENSEM1input
Where READ_VOUT returns VSENSEP – VSENSEM
V
IN
V
V
IN
4.5V < V
< 15V
IBUS
V
V
IN_SNS
PWR
OUT
0.1µF
0.1µF
0.1µF
V
DACP0
R30
DC/DC
CONVERTER
V
V
V
V
SENSEP0
DD33
DD33
DD25
R40
R50
C10
C20
R20
R10
LTC2978*
GND
V
LOAD
FB
V
SENSEM0
V
SGND
DACM0
V
RUN/SS
OUT_EN0
GND
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF EIGHT CHANNELS SHOWN
2978 F28
Figure 28. Antialiasing Filter on VSENSE Lines
4.5V < V
< 15V
IBUS
V
V
IN_SNS
PWR
LTC2978
1.23V TYP
0.1µF
REFP
REFM
SDA
V
SENSEP1
SCL
PMBus
INTERFACE
1µA AT 0.5V
0.1µF
R1 = 4.99k
R2 = 120k
ALERTB
CONTROL
V
SENSEM1
WDI/RESETB
FAULTB
V
= –12V
EE
SHARE_CLK
ASEL0
POWER_GOOD_ON = 0.5V FOR V POWER_GOOD = –11.414V
EE
PWRGD
WHERE V POWER_GOOD =
EE
ASEL1
ONLY ONE OF EIGHT CHANNELS SHOWN,
SOME DETAILS OMITTED FOR CLARITY
WDI/RESETB
WP GND
2978 F29
Figure 29. Sensing Negative Voltages
2978fc
73
LTC2978
APPLICATIONS INFORMATION
2
Connecting the USB to I C/SMBus/PMBus Controller
Figures 30 and 31 illustrate application schematics for
powering, programming and communicating with one or
to the LTC2978 in System
2
more LTC2978's via the LTC I C/SMBus/PMBus controller
2
The LTC USB to I C/SMBus/PMBus Controller can be
regardless of whether or not system power is present.
interfaced to LTC2978s on the user's board for program-
ming, telemetry and system debug. The controller, when
used in conjunction with LTpowerPlay software, provides
a powerful way to debug an entire power system. Failures
arequicklydiagnosedusingtelemetry,faultstatusregisters
and the fault log. The final configuration can be quickly
developed and stored to the LTC2978's EEPROM.
Figure30showstherecommendedschematictousewhen
the LTC2978 is powered by the system intermediate bus
through its V
pin.
PWR
REPEAT OUTLINED CIRCUIT FOR EVERY LTC2978
4.5V TO 15V
150k
49.9k
V
PWR
0.1µF
LTC2978
ISOLATED 3.3V
V
V
DD33
DD33
SCL
Si1303
GND
0.1µF
0.1µF
SDA
V
DD25
TO LTC USB TO
I C/SMBUS/PMBUS
CONTROLLER
PIN CONNECTIONS
OMITTED FOR
CLARITY
2
10k
10k
5.49k
SCL
SDA
SHARE_CLK
WP GND
TO/FROM OTHER
LTC2978s
2978 F30
Figure 30. LTC Controller Connections When VPWR is Used
2978fc
74
LTC2978
APPLICATIONS INFORMATION
Figure31showstherecommendedschematictousewhen
the LTC2978 is powered by the system 3.3V through its
node because this will interfere with bus communication
in the absence of system power.
V
and V
pins. The LTC4212 ideal OR'ing circuit
PWR
2
DD33
The LTC controller's I C/SMBus connections are opto-
allowseitherthecontrollerorsystemtopowertheLTC2978.
isolated from the PC's USB. The 3.3V from the controller
and the LTC2978's V
pin can be paralleled because
Because of the controller's limited current sourcing capa-
bility, onlytheLTC2978s, theirassociatedpullupresistors
DD33
the LTC LDOs that generate these voltages can be back-
driven and draw <10μA. The controller's 3.3V current
limit is 100mA.
2
and the I C/SMBus pull-up resistors should be powered
fromtheORed3.3Vsupply.Inaddition,anydevicesharing
2
I C/SMBus bus connections with the LTC2978 should not
have body diodes between the SDA/SCL pins and its V
DD
IDEAL
DIODE
0R’d 3.3V
TP0101K-SSOT23
SYSTEM
LTC2978_3.3V
V
V
V
V
PWR
DD33
DD33
DD25
3.3V
LTC4412
10k
10k 5.49k
0.1µF
V
SENSE
GATE
STAT
IN
0.1µF
GND
CTL
LTC2978
PIN CONNECTIONS
OMITTED FOR
CLARITY
ISOLATED 3.3V
SCL
SCL
GND
SDA
SHARE_CLK
SDA
WP GND
2978 F31
TO LTC USB TO
I C/SMBUS/PMBUS
CONTROLLER
TO/FROM OTHER
LTC2978s
2
2
NOTE: LTC CONTROLLER I C CONNECTIONS ARE OPTO-ISOLATED
ISOLATED 3.3V FROM CONTROLLER CAN BE BACK DRIVEN AND WILL ONLY DRAW < 10µA
ISOLATED 3.3V CURRENT LIMIT = 100mA
Figure 31. LTC Controller Connections When LTC2978 Powered Directly from 3.3V
2978fc
75
LTC2978
APPLICATIONS INFORMATION
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
during board bring-up to program or tweak the power
management scheme in a system or to diagnose power
issues when bringing up rails. LTpowerPlay utilizes Linear
LTpowerPlay is a powerful Windows based development
environmentthatsupportsLinearTechnologydigitalpower
ICs with EEPROM, including the LTC2978 octal digital
power supply manager. The software supports a variety
of different tasks. You can use LTpowerPlay to evaluate
Linear Technology ICs by connecting to a demo board
system. LTpowerPlay can also be used in an offline mode
(with no hardware present) in order to build a multi-chip
configuration file that can be saved and reloaded at a later
time. LTpowerPlay provides unprecedented diagnostic
and debug features. It becomes a valuable diagnostic tool
2
Technology's USB-to-I C/SMBus/PMBus Controller to
communicate with one of many potential targets, includ-
ing the DC1540 demo board set, the DC1508 socketed
programming board, or a customer target system. The
softwarealsoprovidesanautomaticupdatefeaturetokeep
the software current with the latest set of device drivers
and documentation. A great deal of context sensitive help
is available within LTpowerPlay along with several tutorial
demos. Complete information is available at:
www.linear.com/ltpowerplay
2978fc
76
LTC2978
APPLICATIONS INFORMATION
PCB ASSEMBLY AND LAYOUT SUGGESTIONS
The proposed stencil design enables out-gassing of the
solderpasteduringreflowaswellasregulatingthefinished
solder thickness.
Bypass Capacitor Placement
The LTC2978 requires 0.1µF bypass capacitors between
PC Board Layout
the V
pins and GND, the V
pin and GND, and the
DD33
DD25
REFP pin and REFM pin. If the chip is being powered from
the V input, then that pin should also be bypassed
to GND by a 0.1µF capacitor. In order to be effective,
these capacitors should be made of high quality ceramic
dielectric such as X5R or X7R and be placed as close to
the chip as possible.
Mechanical stress on a PC board and soldering-induced
stress can cause the LTC2978’s reference voltage and
voltage drift to shift. A simple way to reduce these stress-
related shifts is to mount the IC near the short edge of the
PC board, or in a corner. The board edge acts as a stress
boundary, or a region where the flexure of the board is
minimal.
PWR
Exposed Pad Stencil Design
Unused ADC Sense Inputs
The LTC2978’s package is thermally and electrically
efficient. This is enabled by the exposed die attach pad
on the under side of the package which must be soldered
down to the PCB or mother board substrate. It is a good
practice to minimize the presence of voids within the
exposed pad inter-connection. Total elimination of voids
is difficult, but the design of the exposed pad stencil is
key. Figure 32 shows a suggested screen print pattern.
Connect all unused ADC sense inputs (V
SENSEMn
or
SENSEPn
V
) to GND. In a system where the inputs are
connected to removable cards and may be left floating
in certain situations, connect the inputs to GND using
100k resistors. Place the 100k resistors before any filter
components, as shown in Figure 33, to prevent loading
of the filter.
V
SENSEP
LTC2978
SENSEP
100k
V
100k
2978 F33
Figure 33. Connecting Unused Inputs to GND
2978 F32
Figure 32. Suggested Screen Pattern for Die Attach Pad
2978fc
77
LTC2978
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
0.70 ±0.05
7.15 ±0.05
7.50 REF
8.10 ±0.05 9.50 ±0.05
(4 SIDES)
7.15 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ± 0.05
R = 0.115
TYP
9 .00 ± 0.10
(4 SIDES)
R = 0.10
TYP
63 64
0.40 ± 0.10
PIN 1 TOP MARK
(SEE NOTE 5)
1
2
PIN 1
CHAMFER
C = 0.35
7.15 ± 0.10
7.50 REF
(4-SIDES)
7.15 ± 0.10
(UP64) QFN 0406 REV C
0.200 REF
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
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78
LTC2978
REVISION HISTORY (Revision history begins at Rev B)
REV
DATE
10/11 All sections revised
3/12 Change MFR_CONFIG name to MFR_CONFIG_LTC2978
DESCRIPTION
PAGE NUMBER
B
1 - 80
C
19, 23,42
Changed text “data log” to “fault log” under EEPROM Related Commands DATA_LOG Comments
Elaborated on ON_OFF_CONFIG command description
Added Unused ADC Sense Inputs section
23
31
77
80
Renumbered Figure 33 to Figure 34
2978fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
79
LTC2978
TYPICAL APPLICATION
0.1µF
3.3V
0.1µF
0.1µF
13 35 34 65 19 18 17 16 15 33 32 14
V
V
V
V
IN
IN
OUT
39
36
60
2
OUT
V
V
V
DACP7
DACP0
R30
R20
R37
R27
DC/DC
CONVERTER
V
DC/DC
CONVERTER
SENSEP0
SENSEP7
V
V
LOAD
LOAD
LOAD
LOAD
LOAD
FB
FB
37
38
3
R10
V
V
V
R17
SENSEM0
DACM0
SENSEM7
61
V
RUN/SS SGND
GND
SGND RUN/SS
GND
DACM7
4
11
V
V
OUT_EN7
OUT_EN0
V
V
IN
40
42
59
64
OUT
V
V
V
DACP6
DACP1
R36
R26
V
DC/DC
CONVERTER
SENSEP1
SENSEP6
V
FB
43
41
1
V
V
V
R16
SENSEM1
DACM1
SENSEM6
58
V
SGND RUN/SS
GND
DACM6
5
10
V
V
OUT_EN6
OUT_EN1
LTC2978
V
V
V
V
IN
IN
OUT
44
46
56
62
OUT
V
V
V
DACP5
DACP2
R32
R22
R35
R25
DC/DC
V
DC/DC
CONVERTER
SENSEP2
SENSEP5
CONVERTER
V
FB
V
LOAD
FB
47
45
63
57
R12
V
V
V
R15
SENSEM2
DACM2
SENSEM5
V
RUN/SS SGND
GND
SGND RUN/SS
GND
DACM5
6
9
V
V
OUT_EN5
OUT_EN2
V
V
IN
50
48
55
52
OUT
V
V
V
DACP4
DACP3
R34
R24
V
DC/DC
CONVERTER
SENSEP3
SENSEP4
V
FB
49
51
53
54
V
V
V
R14
SENSEM3
DACM3
SENSEM4
V
SGND RUN/SS
GND
DACM4
IN
OUT
7
8
INTERMEDIATE
V
V
OUT_EN4
OUT_EN3
2978 F34
BUS
CONVERTER
12 23 24 25 26 21 27 28 29 30 31 20
10k
22
EN
10k
10k
10k
10k
10k
10k
3.3V
3.3V
10k
10k
10k
10k
5.49k
TO/FROM OTHER LTC2974s, LTC2978s AND MICROCONTROLLER
Figure 34. LTC2978 Application Circuit with 3.3V Chip Power
RELATED PARTS
PART NUMBER
LTC2970
DESCRIPTION
COMMENTS
2
Dual I C Power Supply Monitor and Margining Controller
LTC2974
Quad Digital Power Supply Manager with EEPROM
Accurate Current Measurement and Supervision
LTC3880
Dual Output PolyPhase® Step-Down DC/DC Controller with
Digital Power System Management
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LT 0412 REV C • PRINTED IN USA
80 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
LINEAR TECHNOLOGY CORPORATION 2009
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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